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參數(shù)資料
| 型號： | LTC2481CDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT I2C 10-DFN |
| 標準包裝： | 121 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC951A-ND - BOARD DELTA SIGMA ADC LTC2481 |
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LTC2481
20
2481fc
APPLICATIONS INFORMATION
While operating with an external conversion clock of a
frequency fEOSC, the LTC2481 provides better than 110dB
normal mode rejection in a frequency range of fEOSC/5120
± 4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/5120
is shown in Figure 10.
Whenever an external clock is not present at the CA0/f0 pin,
the converter automatically activates its internal oscillator
and enters the Internal Conversion Clock mode. CA0/f0
may be tied HIGH or left oating in order to set the chip
address. The LTC2481 operation will not be disturbed if
the change of conversion clock source occurs during the
sleep state or during the data output state while the con-
verter uses an external serial clock. If the change occurs
during the conversion state, the result of the conversion in
progress may be outside specications but the following
conversions will not be affected.
Table 6 summarizes the duration of the conversion state
of each state and the achievable output data rate as a
function of fEOSC.
Ease of Use
The LTC2481 data output has no latency, lter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2481 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2481 automatically enters an internal reset
state when the power supply voltage VCC drops below
approximately 2V. This feature guarantees the integrity of
the conversion result.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR signal,
the LTC2481 starts a normal conversion cycle and follows
the succession of states described in Figure 1. The rst
Figure 10. LTC2481 Normal Mode Rejection When
Using an External Oscillator
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
–12
–8
–4
0
4
8
12
NORMAL
MODE
REJECTION
(dB)
2481 F10
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
Table 6. LTC2481 State Duration
STATE
OPERATING MODE
DURATION
CONVERSION
Internal Oscillator
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode 67ms,
Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode 80ms,
Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode 73.6ms,
Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
External Oscillator
CA0/f0 = External Oscillator
with Frequency fEOSC Hz
(fEOSC/5120 Rejection)
41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s for 1x Speed Mode
20556/fEOSCs, Output Data Rate ≤ fEOSC/20556 Readings/s for 2x Speed Mode
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