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參數(shù)資料
| 型號： | LTC2481CDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/40頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT I2C 10-DFN |
| 標準包裝： | 121 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC951A-ND - BOARD DELTA SIGMA ADC LTC2481 |
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LTC2481
12
2481fc
CONVERTER OPERATION
Converter Operation Cycle
The LTC2481 is a low power,
ΔΣanalog-to-digitalconverter
with an I2C interface. After power on reset, its operation
is made up of three states. The converter operating cycle
begins with the conversion, followed by the low power sleep
state and ends with the data output/input (see Figure 1).
The device will not acknowledge an external request during
the conversion state. After a conversion is nished, the
device is ready to accept a read/write request. Once the
LTC2481isaddressedforareadoperation,thedevicebegins
outputting the conversion result under control of the serial
clock (SCL). There is no latency in the conversion result.
The data output is 24 bits long and contains a 16-bit plus
sign conversion result plus a readback of the conguration
bits corresponds to the conversion just performed. This
result is shifted out on the SDA pin under the control of the
SCL. Data is updated on the falling edges of SCL allowing
the user to reliably latch data on the rising edge of SCL.
In write operation, the device accepts one conguration
byte and the data is shifted in on the rising edges of the
SCL. A new conversion is initiated by a STOP condition
following a valid write operation or at the conclusion of a
data read operation (read out all 24 bits).
I2C INTERFACE
The LTC2481 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting
multiple devices and masters on a single bus. The
connected devices can only pull the bus wires LOW and
can never drive the bus HIGH. The bus wires are externally
connected to a positive supply voltage via a current-
source or pull-up resistor. When the bus is free, both
lines are HIGH. Data on the I2C-bus can be transferred
at rates of up to 100kbit/s in the Standard-mode and up
to 400kbit/s in the Fast-mode. The VCC power should not
be removed from the device when the I2C bus is active to
avoid loading the I2C bus lines through the internal ESD
protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate as either
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the clock
signals to permit that transfer. At the same time any device
addressed is considered a slave.
APPLICATIONS INFORMATION
Initially, the LTC2481 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as it is not addressed for a read/write opera-
tion. The conversion result is held indenitely in a static
shift register while the converter is in the sleep state.
Figure 1. LTC2481 State Transition Diagram
CONVERSION
POWER ON RESET
DEFAULT CONFIGURATION:
EXTERNAL INPUT GAIN = 1
50/60Hz REJECTION
1X SPEED, AUTOCAL
SLEEP
2481 F01
YES
NO
ACKNOWLEDGE
YES
NO
STOP
OR READ
24-BITS
DATA OUTPUT/INPUT
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