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參數(shù)資料
| 型號(hào)： | LTC2480IMS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | PLASTIC, MSOP-10 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大小： | 601K |
| 代理商： | LTC2480IMS |
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23
LTC2480
2480fa
APPLICATIO S I FOR ATIO
WU
UU
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time tEOCtest
after the falling edge of CS (if EOC = 0) or tEOCtest after EOC
goes LOW (if CS is LOW during the falling edge of EOC).
The value of tEOCtest is 12s if the device is using its internal
oscillator. If FO is driven by an external oscillator of
frequency fEOSC, then tEOCtest is 3.6/fEOSC in seconds. If CS
is pulled HIGH before time tEOCtest, the device returns to
the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 24th rising edge. The input data is shifted in via
the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 24th rising edge of
SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
CS remains LOW during the data output state. However,
the data output state may be aborted by pulling CS HIGH
anytime between the first and 24th rising edge of SCK (see
Figure 9). On the rising edge of CS, the device aborts the
data output state and immediately initiates a new conver-
sion. If the device has not finished loading the last input bit
SPD of SDI by the time CS is pulled HIGH, the SDI
information is discarded and the previous configuration is
still kept. This is useful for systems not requiring all 24 bits
of output data, aborting an invalid conversion cycle, or
synchronizing the start of a conversion. If CS is pulled
HIGH while the converter is driving SCK LOW, the internal
pull-up is not available to restore SCK to a logic HIGH state.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS HIGH when SCK is LOW.
Figure 8. Internal Serial Clock, Single Cycle Operation
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SDI*
DON’T CARE
SDO
SCK
(INTERNAL)
CS
MSB
SIG
BIT 0
LSB
IM
BIT 4
TEST EOC
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
SLEEP
DATA OUTPUT
CONVERSION
2480 F08
<tEOCtest
Hi-Z
TEST EOC
VCC
FO
VREF
IN+
IN–
SCK
SDI
SDO
CS
GND
210
INT/EXT CLOCK
3
4
5
9
10k
VCC
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUT
1
F
2.7V TO 5.5V
LTC2480
4-WIRE
SPI INTERFACE
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