參數(shù)資料
型號(hào): LTC1966MPMS8#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 26/38頁(yè)
文件大小: 391K
描述: IC RMS/DC CONV MICROPWR 8-MSOP
標(biāo)準(zhǔn)包裝: 2,500
電流 - 電源: 155µA
電源電壓: 2.7 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 帶卷 (TR)
LTC1966
26
1966fb
applicaTions inForMaTion
Input Impedance
The LTC1966 true RMS-to-DC converter utilizes a 2.5pF
capacitor to sample the input at a nominal 100kHz sample
frequency. This accounts for the 8M?input impedance.
See Figure 24 for the equivalent analog input circuit. Note
however, that the 8M?input impedance does not directly
affect the input sampling accuracy. For instance, if a 100k
source resistance is used to drive the LTC1966, the sampling
action of the input stage will drag down the voltage seen
at the input pins with small spikes at every sample clock
edge as the sample capacitor is connected to be charged.
The time constant of this combination is small, 2.5pF "
100k?= 250ns, and during the 2.5祍 period devoted to
sampling, ten time constants elapse. This allows each
sample to settle to within 46ppm and it is these samples
that are used to compute the RMS value.
This is a much higher accuracy than the LTC1966 conver-
sion limits, and far better than the accuracy computed via
the simplistic resistive divider model:
 
V  V
R
R  R
V
M
M    k
V
IN  SOURCE
IN
IN  SOURCE
SOURCE
R E
=
+
=
+   
=
8
8   100
125
 . %
Figure 24. LTC1966 Equivalent Analog Input Circuit
This resistive divider calculation does give the correct
model of what voltage is seen at the input terminals by a
parallel load averaged over a several clock cycles, which is
what a large shunt capacitor will doaverage the current
spikes over several clock cycles.
When high source impedances are used, care must be taken
to minimize shunt capacitance at the LTC1966 input so as
not to increase the settling time. Shunt capacitance of just
2.5pF will double the input settling time constant and the
error in the above example grows from 46ppm to 0.67%
(6700ppm). A 13pF scope probe will increase the error
to almost 20%. As a consequence, it is important to not
try to filter the input with large input capacitances unless
driven by a low impedance. Keep time constant <<2.5祍.
When the LTC1966 is driven by op amp outputs, whose low
DC impedance can be compromised by sharp capacitive
load switching, a small series resistor may be added. A
10k resistor will easily settle with the 2.5pF input sampling
capacitor to within 1ppm.
These are important points to consider both during design
and debug. During lab debug, and even production testing,
a high value series resistor to any test point is advisable.
Output Impedance
The LTC1966 output impedance during operation is simi-
larly due to a switched capacitor action. In this case, 59pF
of on-chip capacitance operating at 100kHz translates into
170k? The closed loop RMS-to-DC calculation cuts that
in half to the nominal 85k?specified.
In order to create a DC result, a large averaging capacitor
is required. Capacitive loading and time constants are not
an issue on the output.
IN1
V
DD
V
DD
V
SS
V
SS
R
SW
 (TYP)
6k
C
EQ
2.5pF
(TYP)
C
EQ
2.5pF
(TYP)
I
IN1
IN2
I
IN2
1966 F24
R
SW
 (TYP)
6k
IIN
V   V
R
IIN
V   V
R
R   M
AVG
IN  IN
EQ
AVG
IN   IN
EQ
EQ
1
2
8
1   2
2   1
(  )
=

( )
=

=
 
&
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