LTC1966
23
1966fb
applicaTions inForMaTion
But with 10?less AC input, the error caused by V
IOS
is
100?larger:
V
OUT
= (20mV AC)
2
+ (0.2mV DC)
2
  = 20.001mV
  = 20mV + 50ppm
This phenomena, although small, is one source of the
LTC1966s residual nonlinearity.
On the other hand, if the input is DC-coupled, the input
offset voltage adds directly. With +200mV and a +0.2mV
V
IOS
, a 200.2mV output will result, an error of 0.1% or
1000ppm. With DC inputs, the error caused by V
IOS
can
be positive or negative depending if the two have the same
or opposing polarity.
The total conversion error with a sine wave input using the
typical values of the LTC1966 static errors is computed
as follows:
V
OUT
= ((500mV AC)
2
+ (0.2mV DC)
2
) " 1.001 + 0.1mV
  = 500.600mV
  = 500mV + 0.120%
V
OUT
= ((50mV AC)
2
+ (0.2mV DC)
2
) " 1.001 + 0.1mV
  = 50.150mV
  = 50mV + 0.301%
V
OUT
= ((5mV AC)
2
+ (0.2mV DC)
2
) " 1.001 + 0.1mV
  = 5.109mV
  = 5mV + 2.18%
As can be seen, the gain term dominates with large inputs,
while the offset terms become significant with smaller
inputs. In fact, 5mV is the minimum RMS level needed to
keep the LTC1966 calculation core functioning normally,
so this represents the worst-case of usable input levels.
Using the worst-case values of the LTC1966 static errors,
the total conversion error is:
V
OUT
= ((500mV AC)
2
+ (0.8mV DC)
2
) " 1.003 + 0.2mV
  = 501.70mV
  = 500mV + 0.340%
V
OUT
= ((50mV AC)
2
+ (0.8mV DC)
2
) " 1.003 + 0.2mV
  = 50.356mV
  = 50mV + 0.713%
V
OUT
= ((5mV AC)
2
+ (0.8mV DC)
2
) " 1.003 + 0.2mV
  = 5.279mV
  = 5mV + 5.57%
These static error terms are in addition to dynamic error
terms that depend on the input signal. See the Design
Cookbook for a discussion of the DC conversion error
with low frequency AC inputs. The LTC1966 bandwidth
limitations cause additional errors with high frequency
inputs. Another dynamic error is due to crest factor. The
LTC1966 performance versus crest factor is shown in the
Typical Performance Characteristics.
Monotonicity and Linearity
The LTC1966, like all implicit RMS-to-DC convertors
(Figure 3), has a division with the output in the denominator.
This works fine most of the time, but when the output is
zero or near zero this becomes problematic. The LTC1966
has multiple switched capacitor amplifier stages, and
depending on the different offsets and their polarity, the
DC transfer curve near zero input can take a few different
forms, as shown in the Typical Performance Characteristics
graph titled DC Transfer Function Near Zero.
Some units (about 1 of every 16) will even be well behaved
with a transfer function that is the upper half of a unit
rectangular hyperbola with a focal point on the y-axis of
a few millivolts.
3
For AC inputs, these units will have a
monotonic transfer function all the way down to zero input.
The LTC1966 is trimmed for offsets as small as practical,
and the resulting behavior is the best statistical linearity
provided the zero region troubles are avoided.
It is possible, and even easy, to force the zero region to
be well behaved at the price of additional (though predict-
able) V
OOS
and some linearity error. For large enough input
signals, this linearity error may be negligible.
3
In general, every LTC1966 will have a DC transfer function that is essentially a unit rectangular
hyperbola (the gain is not always exactly unity, but the gain error is small) with an X- and
Y- offset equal to V
IOS
and V
OOS
, respectively, until the inputs are small enough that the delta
sigma section gets confused. While some units will be the north half of a north south pair, other
units will have two upper halfs of the conjugate, east west, hyperbolas. The circuit of Figure 23
will assure a continuous transfer function.