參數(shù)資料
型號: LTC1966MPMS8#TRPBF
廠商: Linear Technology
文件頁數(shù): 11/38頁
文件大小: 391K
描述: IC RMS/DC CONV MICROPWR 8-MSOP
標準包裝: 2,500
電流 - 電源: 155µA
電源電壓: 2.7 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-MSOP
包裝: 帶卷 (TR)
LTC1966
11
1966fb
applicaTions inForMaTion
How an RMS-to-DC Converter Works
Monolithic RMS-to-DC converters use an implicit com-
putation to calculate the RMS value of an input signal.
The fundamental building block is an analog multiply/
divide used as shown in Figure 3. Analysis of this topol-
ogy is easy and starts by identifying the inputs and the
output of the lowpass filter. The input to the LPF is the
calculation from the multiplier/divider; (V
IN
)
2
/V
OUT
. The
lowpass filter will take the average of this to create the
output, mathematically:
 
V
V
V
V
V
V
so
V
V
V
and
V    V  or
V    V   RMSV
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT    IN
OUT    IN
IN
=
(   )
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
( )
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
( )
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
( )
?/DIV>
?/DIV>
?/DIV>
?/DIV>
(  )
=
( )
=
( )
=
( )
2
2
2
2
2    2
2
,
,
,
,
Because V   is DC,
V
OUT
IN
How the LTC1966 RMS-to-DC Converter Works
The LTC1966 uses a completely new topology for RMS-
to-DC conversion, in which a S modulator acts as the
divider, and a simple polarity switch is used as the multiplier
as shown in Figure 4.
Figure 3. RMS-to-DC Converter with Implicit Computation
Unlike the prior generation RMS-to-DC converters, the
LTC1966 computation does NOT use log/antilog circuits,
which have all the same problems, and more, of log/antilog
multipliers/dividers, i.e., linearity is poor, the bandwidth
changes with the signal amplitude and the gain drifts with
temperature.
Figure 4. Topology of LTC1966
The S modulator has a single-bit output whose average
duty cycle (D) will be proportional to the ratio of the input
signal divided by the output. The S is a 2nd order modula-
tor with excellent linearity. The single bit output is used to
selectively buffer or invert the input signal. Again, this is a
circuit with excellent linearity, because it operates at only
two points: ? gain; the average effective multiplication
over time will be on the straight line between these two
points. The combination of these two elements again creates
a lowpass filter input signal proportional to (V
IN
)
2
/V
OUT
,
which, as shown above, results in RMS-to-DC conversion.
The lowpass filter performs the averaging of the RMS
function and must be a lower corner frequency than the
lowest frequency of interest. For line frequency measure-
ments, this filter is simply too large to implement on-chip,
but the LTC1966 needs only one capacitor on the output
to implement the lowpass filter. The user can select this
capacitor depending on frequency range and settling time
requirements, as will be covered in the Design Cookbook
section to follow.
This topology is inherently more stable and linear than
log/antilog implementations primarily because all of the
signal processing occurs in circuits with high gain op amps
operating closed loop.
V
IN
V
OUT
1966 F03
?nbsp ?/DIV>
LPF
V
V
IN
OUT
(  )
2

REF
V
IN
V
OUT
LPF
?
D
V
V
IN
OUT
?/DIV>
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