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參數(shù)資料
| 型號： | LTC1704EGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 347K |
| 描述： | IC REG DL BUCK/LINEAR 16SSOP |
| 標準包裝： | 2,500 |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 550kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 控制器 |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 3.15 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
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LTC1704/LTC1704B
15
1704bfa
APPLICATIO S I FOR ATIO
U
U
U
across the inductor will be zero, and the inductor current
remains zero. This prevents current from flowing back-
wards in QB, eliminating that power loss term. It also
reduces the ripple current in the inductor as the output
current approaches zero.
The burst comparator is turned on only at the last 180ns
of the switching period, the propagation delay of the
comparator is designed to be fast so that a zero or low
positive voltage on the SW node can trip the comparator
within this 180ns. Low inductor ripple current coupled
with low MOSFET R
DS(ON)
may prolong the delay of the
burst comparator and prevent the comparator from trip-
ping. To overcome this, reduce the inductor value to
increase the ripple current and the SW node voltage
change.
The moment LTC1704 (non-B parts) enters Burst Mode
operation, both drivers skip several switching cycles until
the output droops. Once the voltage feedback loop requests
for an additional 10% duty cycle, the LTC1704 enters Con-
tinuous mode operation again. To eliminate audible noise
from certain types of inductors when they are lightly loaded,
LTC1704 includes an internal timer that forces Continuous
mode operation every 15祍.
In Burst Mode operation, both resistive loss and switching
loss are minimized while keeping the output in regulation.
The total deviation from the regulated output is within the
1.5% regulation tolerance of the LTC1704. As the load
current falls to zero in Burst Mode operation, the most
significant loss term becomes the 4.5mA quiescent cur-
rent drawn by the LTC1704usually much less than the
minimum load current in a typical low voltage logic sys-
tem. Burst Mode operation maximizes efficiency at low load
currents, but can cause low frequency ripple in the output
voltage as the cycle-skipping circuitry switches on and off.
I
RIPPLE
TIME
I
AVERAGE
I
AVERAGE
I
I
RIPPLE
TIME
1704 F05
The LTC1704B does not shift into Burst Mode operation at
light loads, eliminating low frequency output ripple at the
expense of light load efficiency.
The LTC1704 detects when the inductor current has
reached zero by monitoring the voltage at the SW pin while
QB is on (see BURST in Block Diagram). Since QB acts like
a resistor, SW should ideally be right at 0V when the
inductor current reaches zero. In reality, the SW node will
ring to some degree immediately after it is switched to
ground by QB, causing some uncertainty as to the actual
moment the average current in QB goes to zero. The
LTC1704 minimizes this effect by turning on the Burst
Comparator only at the last 180ns of the switching period,
before QB turns off. In addition, the Burst Comparator is
disabled if QB turns on for less than 200ns. Despite this,
care must still be taken in the PCB layout to ensure that
proper kelvin sensing for the SW pin is provided. Connect
the SW pin of the LTC1704 as close to the drain of QB as
possible through a thick trace. The same applies to the
PGND pin of the LTC1704, which is the negative input of
the burst comparator and it should be connected close to
the source of QB through a thick trace. Ringing on the
PGND pin due to an insufficient PV
CC
bypass capacitor can
also cause the burst comparator to trip prematurely.
Connect at least a 10礔 bypass capacitor directly from the
PV
CC
pin to PGND.
BURST
COMPARATOR
DISABLED IF QB
TURNS ON FOR
LESS THAN 200ns
BURST
COMPARATOR
TURNS ON
180ns BEFORE
QB TURNS OFF
TIME
V
SW
0V
5V
0V
V
BG
TIME
1704 F06
Figure 6. Burst Comparator Turns On 180ns Before QB Turns Off
Figure 5a. Continous Mode
Figure 5b. Burst Mode Operation
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