參數(shù)資料
型號: LT5554IUH#PBF
廠商: Linear Technology
文件頁數(shù): 13/32頁
文件大?。?/td> 0K
描述: IC VGA DIG CONTROL 32-QFN
標準包裝: 73
應(yīng)用: 可變增益(VGA)
電路數(shù): 1
-3db帶寬: 1GHz
電流 - 電源: 200mA
電壓 - 電源,單路/雙路(±): 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 管件
產(chǎn)品目錄頁面: 1322 (CN2011-ZH PDF)
LT5554
20
5554f
All seven PGx gain control inputs and STROBE input can
be congured as DC-coupled or ac-coupled. Accordingly,
there are two basic equivalent schematics (shown in Figures
8 and 9) depending on MODE input choice (Table1).
Each PGx input circuit shown in Figures 8 and 9 is fol-
lowed by a transparent latch controlled by the STROBE
input level (Table 1).
The DC-coupled interface is shown in Figure 8. DC levels for
PGx inputs and STROBE input are VIL <0.6V, VIH >2.2V.
The AC-coupled interface is shown in Figure 9. The PGx
inputs and STROBE input state is decided by a signal
transition rather than signal level.
A HIGH-state is set by positive transitions. A LOW-state is
set by negative transitions. The PGx and STROBE inputs
appear as capacitive coupled inputs. The DC voltage (0V
to VCC range) presented on any PGx or STROBE input is
shifted to the internal 1.4V level by the additional circuit
shown in Figure 9. Each PGx and STROBE input has an
independent shift circuit such that each input can have a
different DC voltage.
Each PGx input has a parallel R-C (R1 = 20k, C1 = 2pF)
with a 40ns time constant. The STROBE input circuit has
R1 = 20k C1 = 3pF and 60ns time constant. An minimum
amplitude of 0.6VP-PisrequiredtotripthePGxandSTROBE
inputs to an appropriate state when the signal period is
less than input time constant. The circuit shown in Figure 8
converts the single-ended external signal to an internal
differential signal. Consequently, when the input is idle for
more than the input time constant, a 0.3VP-P transition
will still trigger the gain control state change. All control
inputs have 200mV hysteresis to insure stable logic levels
when the input noise level is less than 100mVP-P.
For transparent latch control, the amplier gain will be
updated directly with any PGx input state changes. If
different PGx inputs have an (external) time skew greater
than 1ns, then a noticeable amplier output glitch can
occur. The strobe latch control is recommended to avoid
this amplier output glitch.
It is not necessary to double buffer the PGx inputs since
the LT5554 has good internal isolation from the PGx inputs
to the amplier output to any type of external gain control
circuit without external components.
If LT5554 is powered up or enabled in latch mode, the
LT5554 gain initial gain is indeterminate. If the minimum
gain state is desired at power up, it is recommended to
set the transparent-mode with all PGx inputs low.
Figure 8. DC-Coupled PGx and STROBE Equivalent Inputs
(Simplied Schematic)
Figure 9. AC-Coupled PGx and STROBE Equivalent Inputs
(Simplied Schematic)
APPLICATIONS INFORMATION
5554 F08
OUT+
OUT
INPUT
VCC
IDC
I1
200μA
V1
1.4V
R3
1.5k
R2
1.5k
Q1
Q3
Q2
R4
20k
R1
20k
C1
2pF
DC-COUPLED
5554 F09
OUT+
OUT
INPUT
VCC
IDC
I1
200μA
V1
1.4V
IDC
AC-COUPLED
I2
IDC
I3
R3
1.5k
R2
1.5k
Q1
Q3
Q2
R4
20k
R1
20k
C1
2pF
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