參數(shù)資料
型號: LT5554IUH#PBF
廠商: Linear Technology
文件頁數(shù): 11/32頁
文件大?。?/td> 0K
描述: IC VGA DIG CONTROL 32-QFN
標(biāo)準(zhǔn)包裝: 73
應(yīng)用: 可變增益(VGA)
電路數(shù): 1
-3db帶寬: 1GHz
電流 - 電源: 200mA
電壓 - 電源,單路/雙路(±): 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 管件
產(chǎn)品目錄頁面: 1322 (CN2011-ZH PDF)
LT5554
19
5554f
APPLICATIONS INFORMATION
The differential outputs can also be converted to single-
ended 50Ω load using a center-tap transformer interface
shown in Figure 6 and Figure 16.
The internal 400Ω differential resistor (RO) sets the output
impedance and the maximum voltage gain (GMAX) to 36dB
when outputs OUT+, OUTare open.
Figure 7 shows the Voltage and Power Gains as a func-
tion of ROUT, which is the total output loading at the open
collector amplier output including the internal resistor
RO = 400Ω.
Voltage clipping will occur with ROUT >140Ω, in which case
the instantaneous voltage at each OUT+ and OUToutputs
is either <2V or >8V.
The output OP1dB = 20dBm can be achieved when ROUT =
130Ω. In this case, the LT5554 outputs reach both current
and voltage limiting for maximum output power.
Gain Control Interface
The MODE pin selects the interface to the LT5554 gain
control pins.
The PGx and STROBE control inputs can be congured
to be either DC-coupled (for TTL interface) or AC-coupled
(for ECL or low-voltage CMOS interfaces).
In addition, the STROBE input can be driven such that the
LT5554 gain state is updated asynchronously (PGx latch
control in transparent-mode) or controlled by positive
STROBE transition (PGx latch control in strobed-mode).
There are several options available for coupling type and
latch control which are given in the following tables:
Table1. MODE Input Options
MODE
(State)
COUPLING TYPE
PGx (Latch Control)
STROBE
PGx
LOW
AC Positive
Transition
AC
Strobe
OPEN
DC >2.2V
AC
Transparent
OPEN
0.6 to 2.2V
AC
Strobe
HIGH
DC >2.2V
DC
Transparent
HIGH
0.6 to 2.2V
DC
Strobe
Table2. MODE Input Levels
MODE
(State)
MODE
(Min Level)
MODE
(Max Level)
LOW
0
0.6V
OPEN
1.5V
2.5V
HIGH
VCC – 0.4V
VCC
Alternatively, the MODE pin can be left open (2V
internal).
Figure 7. Maximum Voltage and Power Gain vs ROUT
The gain vs ROUT relationship is given by the following
equations:
GV = 20log(GM ROUT) in dB
GP = 10log(RIN GM2 ROUT) in dB
Where RIN = 50Ω and GM = 0.15 siemens at GMAX
For wide band applications, the amplier bandwidth can
be extended by inductive peaking technique. The inductor
in series with the LT5554 outputs (OUT+ OUT) can have
a value up to some tens of nH depending on ROUT value
and board capacitance.
The current limiting will occur with ROUT <140Ω, in which
case the instantaneous signal current at the output exceeds
IODC = 45mA.
ROUT (Ω)
10
MAXIMUM
GAIN
(dB)
36
30
24
18
12
6
0
100
400
50
5554 F07
1000
VOLTAGE GAIN
POWER GAIN
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