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參數(shù)資料
| 型號： | LT2435IGN#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 458K |
| 代理商： | LT2435IGN#PBF |
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LTC2435/LTC2435-1
28
24351fb
APPLICATIO S I FOR ATIO
WU
U
Figure 21. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 22. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
±10nA max), results
in a small offset shift. A 100
Ω source resistance will create
a 0.1
μV typical and 1μV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2435/LTC2435-1 sample the
differential reference pins REF+ and REF– transferring
small amount of charge to and from the external driving
circuits thus producing a dynamic reference current. This
current does not change the converter offset, but it may
degrade the gain and INL performance. The effect of this
current can be analyzed in the same two distinct situa-
tions.
For relatively small values of the external reference capaci-
tors (CREF < 0.01μF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01μF) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. For the LTC2435,
when FO = LOW (internal oscillator and 60Hz notch), the
typical differential reference resistance is 15.6M
Ω which
will generate a +FS gain error of approximately 0.032ppm
for each ohm of source resistance driving REF+ or REF–.
When FO = HIGH (internal oscillator and 50Hz notch), the
typical differential reference resistance is 18.7M
Ω which
will generate a +FS gain error of approximately 0.027ppm
for each ohm of source resistance driving REF+ or REF–.
For the LTC2435-1, the typical differential reference resis-
tance is 17.1M
Ω which will generate a +FS gain error of
approximately 0.029ppm for each ohm of source resis-
tance driving REF+ or REF–. When FO is driven by an
external oscillator with a frequency fEOSC (external conver-
sion clock operation), the typical differential reference
resistance is 2.4 1012/fEOSCΩ and each ohm of source
resistance driving REF+ or REF– will result in
0.21 10–6 fEOSCppm +FS gain error. The effect of the
source resistance on the two reference pins is additive
with respect to this gain error. The typical +FS and –FS
errors for various combinations of source resistance seen
by the REF+ and REF– pins and external capacitance CREF
connected to these pins are shown in Figures 21, 22, 23
and 24.
RSOURCE (Ω)
1
+FS
ERROR
VARIATION
(ppm)
100
90
80
70
60
50
40
30
20
10
0
–10
10000
2435 F21
10
100
1000
100000
CIN = 0pF
CIN = 0.01μF
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
CIN = 100pF
CIN = 0.001μF
RSOURCE (Ω)
1
–FS
ERROR
VARIATION
(ppm)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10000
2435 F22
10
100
1000
100000
CIN = 0pF
CIN = 0.01μF
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
CIN = 0.001μF
CIN = 100pF
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