參數(shù)資料
型號： LT2435IGN#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16
文件頁數(shù)： 14/40頁
文件大?。?/td> 458K
代理商： LT2435IGN#PBF
LTC2435/LTC2435-1
21
24351fb
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state. In order to allow the device to return to the sleep
state, CS must be pulled HIGH before the first rising edge
of SCK. In the internal SCK timing mode, SCK goes HIGH
and the device begins outputting data at time tEOCtest after
the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes
LOW (if CS is LOW during the falling edge of EOC). The
value of tEOCtest is 23μs (LTC2435), 26μs (LTC2435-1) if
the device is using its internal oscillator (F0 = logic LOW or
APPLICATIO S I FOR ATIO
WU
U
Figure 10. External Serial Clock, CS = 0 Operation (2-Wire)
Figure 11. Internal Serial Clock, Single Cycle Operation
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
MSB
LSB
SIG
BIT 0
BIT 5
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
DATA OUTPUT
CONVERSION
2435 F10
CONVERSION
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
214
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
2-WIRE
INTERFACE
1
μF
2.7V TO 5.5V
LTC2435/
LTC2435-1
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
VCC
SDO
SCK
(INTERNAL)
CS
MSB
LSB
SIG
BIT 0
BIT 5
TEST EOC
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
EOC
BIT 23
SLEEP
DATA OUTPUT
CONVERSION
2435 F11
<tEOCtest
VCC
10k
Hi-Z
TEST EOC
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
214
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE
1
μF
2.7V TO 5.5V
LTC2435/
LTC2435-1
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
VCC
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