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參數(shù)資料
| 型號： | LT1939IDD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 349K |
| 描述： | IC REG DL BUCK/LINEAR 12DFN |
| 標準包裝： | 2,500 |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 500kHz ~ 2.4MHz |
| 電壓/電流 - 輸出 1： | 0.8 V ~ 24.25 V，2A |
| 電壓/電流 - 輸出 2： | 0.8 V ~ 24.25 V，1A |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 3 V ~ 25 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 12-DFN |
| 包裝： | 帶卷 (TR) |
LT1939
18
1939f
the synchronization circuitry to the LT1939 as shown in
the Typical Applications section. This will allow the LT1939
to start up with a switching frequency determined by the
equivalent resistance from the R
T
/SYNC pin to ground.
Shutdown and Undervoltage Lockout
Figure 8 shows how to add an undervoltage lockout (UVLO)
to the LT1939. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
R2=
0.76
V
H
0.76
R
1
+2.5?/DIV>
A
V
H
= Turn-on threshold
V
L
= Turn-off threshold
Example: switching should not start until the input is above
4.75V and is to stop if the input falls below 3.75V.
V
H
= 4.75V
V
L
= 3.75V
R1=
4.753.75
2?/DIV>
A
~499k
R2=
0.76
4.750.76
499
k
+2.5?/DIV>
A
~71.5k
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to switching nodes is minimized. If high re-
sistor values are used, the SHDN pin should be bypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
Soft-Start
The outputs of the LT1939 regulate to either the SS pin
voltage minus 100mV or an internally regulated 800mV,
whichever is lowest. A capacitor from the SS pin to ground
is charged by an internal 2.75糀 current source resulting
in a linear output ramp from 0V to the regulated output
whose duration is given by:
t
RAMP
=
C
SS
"0.9V
2.75?/DIV>
A
At power-up, a reset signal sets the soft-start latch and
discharges the SS pin to approximately 0V to ensure
proper start-up. When the SS pin is fully discharged the
latch is reset and the internal 2.75糀 current source starts
to charge the SS pin.
APPLICATIONS INFORMATION
Figure 8. Undervoltage Lockout
An internal comparator will force the part into shutdown
below the minimum V
IN
of 2.8V. This feature can be
used to prevent excessive discharge of battery-operated
systems.
If an adjustable UVLO threshold is required, the SHDN
pin can be used. The threshold voltage of the SHDN pin
comparator is 0.76V. A 2.5糀 internal current source de-
faults the open-pin condition to be operating (see Typical
Performance Characteristics). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
R1=
V
H
V
L
2?/DIV>
A
+
0.76V
2糀
2.5糀
R1
R2
C1
SHDN
V
IN
1939 F08
1
2
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