參數(shù)資料
型號: LT1719IS8#PBF
廠商: Linear Technology
文件頁數(shù): 8/22頁
文件大?。?/td> 0K
描述: IC COMP R-RINOUT SINGLE 8-SOIC
標準包裝: 100
系列: UltraFast™
類型: 通用
元件數(shù): 1
輸出類型: CMOS,滿擺幅,TTL
電壓 - 電源,單路/雙路(±): 2.7 V ~ 6 V
電壓 - 輸入偏移(最小值): 2.5mV @ ±5V
電流 - 輸入偏壓(最小值): 6µA @ ±5V
電流 - 輸出(標準): 20mA
電流 - 靜態(tài)(最大值): 9mA
CMRR, PSRR(標準): 70dB CMRR,80dB PSRR
傳輸延遲(最大): 4.2ns
磁滯: 7mV
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 管件
LT1719
16
1719fa
Circuit Description
The block diagram of the LT1719 is shown in Figure 7.
The circuit topology consists of a differential input stage,
a gain stage with hysteresis and a complementary com-
mon-emitter output stage. All of the internal signal paths
utilize low voltage swings for high speed at low power.
The input stage topology maximizes the input dynamic
range available without requiring the power, complexity
and die area of two complete input stages such as are
found in rail-to-rail input comparators. With a single
2.7V supply, the LT1719 still has a respectable 1.6V of
input common mode range. The differential input volt-
age range is rail-to-rail, without the large input currents
found in competing devices. The input stage also features
phase reversal protection to prevent false outputs when
the inputs are driven below the –100mV common mode
voltage limit.
The internal hysteresis is implemented by positive, nonlin-
ear feedback around a second gain stage. Until this point,
the signal path has been entirely differential. The signal
path is then split into two drive signals for the upper and
lower output transistors. The output transistors are con-
nected common emitter for rail-to-rail output operation.
The Schottky clamps limit the output voltages at about
300mV from the rail, not quite the 50mV or 15mV of Linear
Technology’s rail-to-rail ampliers and other products. But
the output of a comparator is digital, and this output stage
can drive TTL or CMOS directly. It can also drive ECL, as
described earlier, or analog loads as demonstrated in the
applications to follow.
The bias conditions and signal swings in the output stage
are designed to turn their respective output transistors off
faster than on. This helps minimize the surge of current from
+VS/V+ to ground that occurs at transitions, to minimize
the frequency-dependent increase in power consumption.
The frequency dependence of the supply current is shown
in the Typical Performance Characteristics.
Speed Limits
The LT1719 comparator is intended for high speed ap-
plications, where it is important to understand a few
limitations. These limitations can roughly be divided into
APPLICATIONS INFORMATION
OUT
GND OR V
+VS OR V
+
+
+
+
+
+IN
–IN
AV1
VCC OR V
+
VEE OR V
SHUTDOWN
AV2
NONLINEAR STAGE
1719 F07
+
+
BIAS CONTOL
Figure 7. LT1719 Block Diagram
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