VREF VTH R3
參數(shù)資料
型號: LT1719IS8#PBF
廠商: Linear Technology
文件頁數(shù): 5/22頁
文件大?。?/td> 0K
描述: IC COMP R-RINOUT SINGLE 8-SOIC
標準包裝: 100
系列: UltraFast™
類型: 通用
元件數(shù): 1
輸出類型: CMOS,滿擺幅,TTL
電壓 - 電源,單路/雙路(±): 2.7 V ~ 6 V
電壓 - 輸入偏移(最小值): 2.5mV @ ±5V
電流 - 輸入偏壓(最小值): 6µA @ ±5V
電流 - 輸出(標準): 20mA
電流 - 靜態(tài)(最大值): 9mA
CMRR, PSRR(標準): 70dB CMRR,80dB PSRR
傳輸延遲(最大): 4.2ns
磁滯: 7mV
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 管件
LT1719
13
1719fa
+
LT1719S8
1719 F05
R2
VREF
VTH
R3
+VS
2
VAVERAGE =
R1
Figure 5. Model for Additional Hysteresis Calculations
With this in mind, calculation of the resistor values needed
is a two-step process. First, calculate the value of R3 based
on the additional hysteresis desired, the output voltage
swing and the impedance of the primary bias string:
R3 = (R1R2)(+VS – 0.6V)/(additional hysteresis)
Additional hysteresis is the desired overall hysteresis less
the internal 4mV hysteresis.
The second step is to recalculate R2 to set the same av-
erage threshold as before. The average threshold before
was set at VTH = (VREF)(R1)/(R1 + R2). The new R2 is
calculated based on the average output voltage (+VS/2)
and the simplied circuit model in Figure 5. To assure
that the comparator’s noninverting input is, on average,
the same VTH as before:
R2 = (VREF – VTH)/(VTH/R1 + [VTH – (+VS)/2]/R3)
For additional hysteresis of 10mV or less, it is not un-
common for R2 to be the same as R2 within 1% resistor
tolerances.
This method will work for additional hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R3 is
low enough to effect the bias string, and adjustment of R1
may also be required. Note that the currents through the
R1/R2 bias string should be many times the input currents
of the LT1719. For 5% accuracy, the current must be at
least 20 times the input current, more for higher accuracy.
This illustration used an LT1719S8; with an LT1719S6 the
same procedure is used with V+ substituted for +VS.
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