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參數(shù)資料
| 型號(hào)： | LT1719IS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP R-RINOUT SINGLE 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | UltraFast™ |
| 類型： | 通用 |
| 元件數(shù)： | 1 |
| 輸出類型： | CMOS，滿擺幅，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 6 V |
| 電壓 - 輸入偏移（最小值）： | 2.5mV @ ±5V |
| 電流 - 輸入偏壓（最小值）： | 6µA @ ±5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 9mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 70dB CMRR，80dB PSRR |
| 傳輸延遲（最大）： | 4.2ns |
| 磁滯： | 7mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 管件 |
LT1719
4
1719fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IS
Positive Output Stage Supply Current
+ VS = VCC = 5V, VEE = –5V
l
4.2
8
mA
(LT1719S8 Only) VS = VCC = 3V, VEE = 0V
l
3.3
6
mA
I+
Supply Current
(LT1719S6) V+ = 5V
l
4.6
9
mA
V+ = 3V
l
4.2
7
mA
ISHDN5
Shutdown Pin Current
+VS or V+ = 5V
l
–300
–110
–30
μA
ISHDN3
Shutdown Pin Current
+VS or V+ = 3V
l
–200
–80
–20
μA
ICCS
ISS
IEES
I+S
ICCSO
ISSO
IEEO
I+O
Disabled Supply Currents (LT1719S8)
(LT1719S8)
(LT1719S6)
(LT1719S8)
(LT1719S6)
+VS = 6V, VCC = 5V, VEE = –5V
VSHDN = +VS – 0.5V
l
–30
0.2
7
–0.2
30
50
μA
V+ = 6V, VSHDN = +VS – 0.5V
l
780
μA
+VS = 6V, VCC = 5V, VEE = –5V
Shutdown Pin Open
l
–20
0.1
20
μA
V+ = 6V, Shutdown Pin Open
l
0.2
40
μA
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. VCM = 1V, VSHDN = 0.5V, VOVERDRIVE = 20mV, COUT = 10pF and for the
LT1719S8 VCC = +VS = 5V and VEE = –5V, for the LT1719S6 V+ = 5V, V– = 0V, unless otherwise specied.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: If one input is within these common mode limits, the other input
can go outside the common mode limits and the output will be valid.
Note 3: The LT1719 comparator includes internal hysteresis. The trip
points are the input voltage needed to change the output state in each
direction. The offset voltage is dened as the average of VTRIP+ and VTRIP–,
while the hysteresis voltage is the difference of these two.
Note 4: The LT1719S8 common mode rejection ratio is measured with
VCC = 5V, VEE = –5V and is dened as the change in offset voltage measured
from VCM = –5.1V to VCM = 3.8V, divided by 8.9V.
Note 5: The LT1719S6 common mode rejection ratio is measured with
V+ = 5V and is dened as the change in offset voltage measured from
VCM = –0.1V to VCM = 3.8V, divided by 3.9V.
Note 6: The LT1719S8 power supply rejection ratio is measured with
VCM = 1V and is dened as the worst of: the change in offset voltage from
VEE = – 5.5V to VEE = 0V divided by 5.5V, or the change in offset voltage
from VCC = +VS = 2.7V to VCC = +VS = 6V (with VEE = 0V) divided by 3.3V.
Note 7: The LT1719S6 power supply rejection ratio is measured with
VCM = 1V and is dened as the change in offset voltage measured from
V+ = 2.7V to V+ = 6V, divided by 3.3V.
Note 8: Because of internal hysteresis, there is no small-signal region in
which to measure gain. Proper operation of internal circuity is ensured by
measuring VOH and VOL with only 10mV of overdrive.
Note 9: Propagation delay measurements made with 100mV steps.
Overdrive is measured relative to VTRIP±.
Note 10: tPD cannot be measured in automatic handling equipment with
low values of overdrive. The LT1719 is 100% tested with a 100mV step
and 20mV overdrive. Correlation tests have shown that tPD limits can be
guaranteed with this test, if additional DC tests are performed to guarantee
that all internal bias conditions are correct.
Note 11: Propagation Delay Skew is dened as:
tSKEW = |tPDLH – tPDHL|
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