參數(shù)資料
型號: LSIFC929X
英文描述: LSIFC929X dual channel fibre solutions
中文描述: LSIFC929X雙通道光纖解決方案
文件頁數(shù): 79/144頁
文件大?。?/td> 1496K
代理商: LSIFC929X
Host Interface Registers
5-23
DSLT[1:0]
Data_Select
The LSIFC909 does not support the data register.
Therefore, these two bits default to 0. The host can
program these bits and the LSIFC909 will retain the
programmed value; however, the value is not used since
the data register is not implemented in the LSIFC909.
[12:9]
PEN
PME_Enable
The LSIFC909 always returns zero for this bit to indicate
that PME assertion is disabled.
8
R
Reserved
[7:2]
PWS[1:0]
Power State
Bits [1:0] are used to determine the current power state
of the LSIFC909. They are used to place the LSIFC909
in a new power state. Power states are defined as:
[1:0]
Registers:0x48–0x7F
Reserved
Read Only
5.7 Host Interface Registers
The first 128 bytes of PCI Memory 0 address space contain the Host
Interface register set as specified in
Table 5.3
. Both 32-bit and 64-bit
accesses are allowed to the Host register set. The LSIFC909 design
supports only nonburst accesses to the Host Interface register set and
will Disconnect-with-data (TRDY/ and STOP/ both asserted) after the first
transfer of any burst attempt.
The LSIFC909 also specifies an I/O space requirement of 128 bytes of
I/O mapped space which the system is required to assign during PCI
configuration. The 128 bytes of I/O space are mapped onto the first
128 bytes of Memory 0 space; they provide an alternate access path to
0b00
0b01
0b10
0b11
D0
D1
D2
D3 hot
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