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參數(shù)資料
| 型號： | lpm-shiftreg |
| 廠商： | Altera Corporation |
| 英文描述： | Parameteruzed Shift Register(參數(shù)確定的移位寄存器) |
| 中文描述： | Parameteruzed移位寄存器（參數(shù)確定的移位寄存器） |
| 文件頁數(shù)： | 34/48頁 |
| 文件大?。?/td> | 293K |
| 代理商： | LPM-SHIFTREG |
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Altera Corporation
29
Storage Functions
lpm_ram_dq
Parameterized Random Access Memory
with Separate Input and Output Ports
The
lpm_ram_dq
function can be used as
either synchronous or asynchronous
random access memory. The
lpm_ram_dq
function has separate input and output data
buses.
Ports
Name
Type
Required
Description
data[]
Input
Input
Input
Yes
Yes
No
Data input to memory. This port is
LPM_WIDTH
wide.
Address input to the memory. This port is
LPM_WIDTHAD
wide.
Synchronizes memory loading. If the
inclock
port is used, the
we
port acts
as an enable for write operations synchronized to the rising edge of the
inclock
input. If the
inclock
port is not used, the
we
port acts as an enable
for asynchronous write operations.
Synchronizes
q[]
outputs from memory. The addressed memory
content
q[]
response is synchronous when the
outclock
port is
connected, and asynchronous when it is not connected.
Write enable input. When high, enables write operation to the memory.
Required if
inclock
is not present. If only
we
is used, the data on the
address[]
port should not change while
we
is high. If the data on the
address[]
port changes while
we
is high, all memory locations that are
addressed are overwritten with
data[]
.
Data output from the memory. This port is
LPM_WIDTH
wide.
address[]
inclock
outclock
Input
No
we
Input
Yes
q[]
Output
Yes
LPM_RAM_DQ
data[]
address[]
inclock
outclock
we
LPM_ADDRESS_CONTROL=
LPM_FILE=
LPM_INDATA=
LPM_NUMWORDS=
LPM_OUTDATA="UNREGISTERED"
LPM_WIDTH=
LPM_WIDTHAD=
q[]
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