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參數(shù)資料
| 型號： | lpm-shiftreg |
| 廠商： | Altera Corporation |
| 英文描述： | Parameteruzed Shift Register(參數(shù)確定的移位寄存器) |
| 中文描述： | Parameteruzed移位寄存器（參數(shù)確定的移位寄存器） |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 293K |
| 代理商： | LPM-SHIFTREG |
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10
Altera Corporation
Gate Functions
lpm_mux
Parameterized Multiplexer
Ports
Parameters
Name
Type
Required
Description
aclr
Input
No
Asynchronous clear for pipelined usage. The pipeline initializes to undefined.
The
aclr
port can be used at any time to reset the pipeline to all 0s,
asynchronously to the clock.
Data input. This port consists of
LPM_SIZE
buses, each
LPM_WIDTH
wide.
Clock for pipelined usage. The clock port provides pipelined operation for
lpm_mux
. For
LPM_PIPELINE
values other than 0 (default value), the
clock
port must be connected.
Selects one of the input buses. This port is
LPM_WIDTHS
wide.
Selected input port. This port is
LPM_WIDTH
wide.
data[][]
Input
Input
Yes
Yes
clock
sel[]
Input
Output
Yes
Yes
result[]
Name
Required
Value
Description
LPM_PIPELINE
No
Integer
≥
0
Specifies the number of clock cycles of latency
associated with the
result[]
output. A value of
zero (0) indicates that no latency exists, and that a
purely combinatorial function will be instantiated.
The default value is 0 (non-pipelined).
LPM_SIZE
Yes
2
LPM_WIDTHS
≥
Integer > 1 Number of inputs to each multiplexer. Number of
input buses.
Integer > 0
Width of the
data[][]
and
result[]
ports.
Integer > 0
Width of the
sel[]
port. The default value is
ceil(log
2
(
LPM_SIZE
)).
LPM_WIDTH
Yes
Yes
LPM_WIDTHS
data[][]
result[]
sel[]
LPM_MUX
clock
aclr
LPM_PIPELINE=
LPM_SIZE=
LPM_WIDTH=
LPM_WIDTHS=CEIL(LOG2(LPM_SIZE))
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