參數(shù)資料
型號(hào)： LPC47M112-MW
廠商： STANDARD MICROSYSTEMS CORP
元件分類(lèi)： 外設(shè)及接口
英文描述： ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
中文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封裝： 14 X 20 MM, ROHS COMPLIANT, QFP-100
文件頁(yè)數(shù)： 6/228頁(yè)
文件大?。?/td> 1269K
代理商： LPC47M112-MW
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SMSC DS – LPC47M192
Page 6
Rev. 03/30/05
DATASHEET
7.18.3.7
7.18.3.8
7.18.3.9
7.18.3.10
7.18.3.11
7.18.3.12
RUNTIME REGISTERS .....................................................................................................................139
Analog Voltage Measurement.......................................................................................................................135
Voltage ID.....................................................................................................................................................135
Temperature Measurement............................................................................................................................135
Thermal / Voltage Interrupt Pin....................................................................................................................136
Input Safety...................................................................................................................................................137
Layout Considerations..................................................................................................................................137
8
9
CONFIGURATION .............................................................................................................................166
9.1
S
YSTEM
E
LEMENTS
........................................................................................................................166
9.1.1
Primary Configuration Address Decoder ..............................................................................................166
9.1.1.1
Entering the Configuration State...................................................................................................................166
9.1.1.2
Exiting the Configuration State.....................................................................................................................166
9.2
C
ONFIGURATION
S
EQUENCE
...........................................................................................................167
9.2.1
Enter Configuration Mode.....................................................................................................................167
9.2.1.1
Configuration Mode......................................................................................................................................167
9.2.2
Exit Configuration Mode .......................................................................................................................167
9.2.2.1
Programming Example..................................................................................................................................167
9.3
C
HIP
L
EVEL
(G
LOBAL
)
C
ONTROL
/C
ONFIGURATION
R
EGISTERS
[0
X
00-0
X
2F].....................................170
9.4
L
OGICAL
D
EVICE
C
ONFIGURATION
/C
ONTROL
R
EGISTERS
[0
X
30-0
X
FF].............................................173
9.5
SMSC
D
EFINED
L
OGICAL
D
EVICE
C
ONFIGURATION
R
EGISTERS
.......................................................178
10
REGISTERS FOR HARDWARE MONITORING BLOCK..............................................................184
10.1
R
EGISTER
S
UMMARY
...................................................................................................................184
10.2
I
NTERNAL
A
DDRESS
R
EGISTER
....................................................................................................184
10.3
V
ALUE OR
L
IMIT
R
EGISTERS
(15
H
-3D
H
).......................................................................................184
10.3.1.1
Registers 3Eh-4Fh.........................................................................................................................................186
11
OPERATIONAL DESCRIPTION.....................................................................................................190
11.1
M
AXIMUM
G
UARANTEED
R
ATINGS
................................................................................................190
11.1.1
Super I/O section (pins 1 to 100).......................................................................................................190
11.1.2
Hardware Monitoring Block (pins 101 to 128) ...................................................................................190
11.2
H
ARDWARE
M
ONITORING
B
LOCK
S
PECIFICATIONS
........................................................................190
11.2.1
Key Specifications.............................................................................................................................190
11.2.2
Supply Current..................................................................................................................................190
11.2.3
Operating Temperature.....................................................................................................................190
11.2.4
Operating Voltage Ratings................................................................................................................190
11.3
DC
E
LECTRICAL
C
HARACTERISTICS
.............................................................................................191
11.3.1
Capacitance values for Pins..............................................................................................................196
12
TIMING DIAGRAMS.......................................................................................................................197
13
PACKAGE OUTLINE......................................................................................................................220
14
APPENDIX A – THERMAL DIODE PARAMETERS......................................................................221
15
APPENDIX B – ADC VOLTAGE CONVERSION...........................................................................222
16
APPENDIX C - TEST MODE..........................................................................................................223
16.1
S
UPER
I/O
B
LOCK
.......................................................................................................................223
16.1.1
Board Test Mode...............................................................................................................................223
16.2
H
ARDWARE
M
ONITORING
B
LOCK
.................................................................................................225
16.2.1
Board Test Mode...............................................................................................................................225
16.2.2
XNOR-Chain Test Mode ...................................................................................................................225
17
APPENDIX D - REFERENCE DOCUMENTS.................................................................................227
18
LPC47M192 REVISIONS................................................................................................................228
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