參數(shù)資料
型號: LPC3250FET296,551
廠商: NXP Semiconductors
文件頁數(shù): 49/57頁
文件大小: 0K
描述: IC ARM9 MCU 256K 296-TFBGA
特色產(chǎn)品: LPC32x0 ARM926EJ-S Processor
標(biāo)準(zhǔn)包裝: 126
系列: LPC3200
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 266MHz
連通性: EBI/EMI,以太網(wǎng),I²C,IrDA,Microwire,SPI,SSI,SSP,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,電機(jī)控制 PWM,PWM,WDT
輸入/輸出數(shù): 51
程序存儲器類型: ROMless
RAM 容量: 256K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 296-TFBGA
包裝: 托盤
配用: 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250
568-4742-ND - MODULE DIMM LPC2478 ARM7
622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250
其它名稱: 568-4533
935287084551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
53 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
10.1 Minimum core voltage requirements
Figure 4 shows the minimum core supply voltage that should be applied for a given core
frequency on pin VDD_CORE to ensure stable operation of the LPC3220/30/40/50.
10.2 Power supply sequencing
The LPC32x0 has no power sequencing requirements, that is, VDD(1V2), VDD(EMC), VDD(IO),
and VDDA(3V3) can be switched on or off independent of each other. An internal circuit
ensures that the system correctly powers up in the absence of core power. During IO
power-up this circuit takes care that the system is powered in a defined mode. The same
is valid for core power-down.
10.3 Power consumption per peripheral
[1]
All three Ethernet clocks are in enabled in the MAC_CLK_CTRL register (see LPC32x0 User manual).
Fig 4.
Minimum required core supply voltage for different core frequencies
core frequency (MHz)
160
280
240
200
002aae872
1.0
1.2
1.4
0.8
VDD_CORE
(V)
Table 9.
Power consumption per peripheral
Tamb =25 C; CPU clock = 208 MHz; I-cache/D-cache, MMU disabled; VDD_CORE = 1.2 V;
VDD(IO) = 1.8 V; USB AHB, IRAM, and IROM clocks always on; all peripherals are at their default
state at reset. Peripheral clocks are disabled except for peripheral measured.
Peripheral
IDD(run) / mA
High-speed UART (set to 115 200 Bd (8N1))
0.3
I2C-bus
0.3
SSP
0.6
I2S0.5
DMA
6.3
EMC
7.3
Multi-level NAND controller
1.4
Single-level NAND controller
0.3
LCD
5.6
Ethernet MAC[1]
2.9
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