參數(shù)資料
型號(hào)： LPC3250FET296,551
廠商： NXP Semiconductors
文件頁數(shù)： 26/57頁
文件大小： 0K
描述： IC ARM9 MCU 256K 296-TFBGA
特色產(chǎn)品： LPC32x0 ARM926EJ-S Processor
標(biāo)準(zhǔn)包裝： 126
系列： LPC3200
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 266MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，電機(jī)控制 PWM，PWM，WDT
輸入/輸出數(shù)： 51
程序存儲(chǔ)器類型： ROMless
RAM 容量： 256K x 8
電壓 - 電源 (Vcc/Vdd)： 0.9 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 296-TFBGA
包裝： 托盤
配用： 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250
568-4742-ND - MODULE DIMM LPC2478 ARM7
622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250
其它名稱： 568-4533
935287084551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
32 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
condition is indicated via status registers. An interrupt is also generated if enabled. The
DMA controller when enabled transfers data between the endpoint buffer and the USB
RAM.
Features
Fully compliant with USB 2.0 full-speed specification.
Supports 32 physical (16 logical) endpoints.
Supports control, bulk, interrupt and isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
RAM message buffer size based on endpoint realization and maximum packet size.
Supports bus-powered capability with low suspend current.
Supports DMA transfer on all non-control endpoints.
One duplex DMA channel serves all endpoints.
Allows dynamic switching between CPU controlled and DMA modes.
Double buffer implementation for bulk and isochronous endpoints.
7.6.3.2
USB host controller
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.
Features
OHCI compliant.
OHCI specifies the operation and interface of the USB host controller and software
driver.
The host controller has four USB states visible to the software driver:
– USBOperational: Process lists and generate SOF tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wake-up activity.
– USBResume: Forces resume signaling on the bus.
HCCA register points to interrupt and isochronous descriptors list.
ControlHeadED and BulkHeadED registers point to control and bulk descriptors list.
7.6.3.3
USB OTG controller
USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals.
Features
Fully compliant with On-The-Go supplement to the USB Specification 2.0 Revision
1.0.
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