參數(shù)資料
型號(hào): LPC2212
廠商: NXP Semiconductors N.V.
英文描述: 16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP Flash with 10-bit ADC and external memory interface
中文描述: 16/32位ARM微控制器; 128/256 kB ISP / IAP閃存的10位模數(shù)轉(zhuǎn)換器和外部存儲(chǔ)器接口
文件頁(yè)數(shù): 22/40頁(yè)
文件大?。?/td> 185K
代理商: LPC2212
Philips Semiconductors
LPC2212/LPC2214
16/32-bit ARM microcontrollers with external memory interface
Product data
Rev. 02 — 23 December 2004
22 of 40
9397 750 13149
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
The I
2
C bus may be used for test and diagnostic purposes.
6.15 SPI serial I/O controller
The LPC2212/LPC2214 each contain two SPIs. The SPI is a full duplex serial
interface, designed to be able to handle multiple masters and slaves connected to a
given bus. Only a single master and a single slave can communicate on the interface
during a given data transfer. During a data transfer the master always sends a byte of
data to the slave, and the slave always sends a byte of data to the master.
6.15.1
Features
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
6.16 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. It also includes four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with
‘or’ and ‘a(chǎn)nd’, as well as ‘broadcast’ functions among them.
6.16.1
Features
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Four external outputs per timer corresponding to match registers, with the following
capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
相關(guān)PDF資料
PDF描述
LPC2214 16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP Flash with 10-bit ADC and external memory interface
LPC2220 16/32-bit ARM microcontrollers; flashless with 64 kB, with 10-bit ADC and external memory interface
LPC2364FB100 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
LPC2364 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
LPC2366 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
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