參數(shù)資料
型號(hào): LPC1751FBD80
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC
中文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN
文件頁(yè)數(shù): 37/74頁(yè)
文件大?。?/td> 1572K
代理商: LPC1751FBD80
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
37 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
8. Limiting values
[1]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless
otherwise noted.
[2]
Including voltage on outputs in 3-state mode.
[3]
Not to exceed 4.6 V.
[4]
The peak current is limited to 25 times the corresponding maximum current.
[5]
Dependent on package type.
[6]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k
series resistor.
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Symbol
Parameter
V
DD(3V3)
supply voltage (3.3 V)
V
DD(REG)(3V3)
regulator supply voltage (3.3 V)
V
DDA
analog 3.3 V pad supply voltage
V
i(VBAT)
input voltage on pin VBAT
V
i(VREFP)
input voltage on pin VREFP
V
IA
analog input voltage
Limiting values
Conditions
external rail
Min
2.4
2.4
0.5
0.5
0.5
0.5
Max
3.6
3.6
+4.6
+4.6
+4.6
+5.1
Unit
V
V
V
V
V
V
for the RTC
on ADC related
pins
5 V tolerant I/O
pins; only valid
when the V
DD(3V3)
supply voltage is
present
other I/O pins
V
I
input voltage
[2]
0.5
+5.5
V
[2][3]
0.5
V
DD(3V3)
+
0.5
100
100
100
V
I
DD
I
SS
I
latch
supply current
ground current
I/O latch-up current
per supply pin
per ground pin
(0.5V
DD(3V3)
) < V
I
< (1.5V
DD(3V3)
);
T
j
< 125
C
[4]
-
mA
mA
mA
[4]
-
-
T
stg
P
tot(pack)
storage temperature
total power dissipation (per package)
[5]
65
-
+150
1.5
C
W
based on package
heat transfer, not
device power
consumption
human body
model; all pins
V
ESD
electrostatic discharge voltage
[6]
4000
+4000
V
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