參數(shù)資料
型號(hào)： LPC12D27FBD100/301
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 8/46頁(yè)
文件大?。?/td> 0K
描述： MCU 32BIT ARM CORTEX-M0 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： LPC1200
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 45MHz
連通性： I²C，IrDA，SPI，SSP，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
其它名稱： 568-8372
LPC12D27
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 20 September 2011
16 of 46
NXP Semiconductors
LPC12D27
32-bit ARM Cortex-M0 microcontroller
7.2.6 Timing
The PCF8576D timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCF8576D in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency (ffr) is a fixed division of the clock frequency (fclk) from either the internal or an
external clock: ffr = fclk/24.
7.2.7 Display register
A display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs, and each column of the display RAM.
7.2.8 Segment outputs
The LCD drive section includes 40 segment outputs S0 to S39 which should be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data residing in the display latch. When less than
40 segment outputs are required, the unused segment outputs should be left open-circuit.
7.2.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals
and may also be paired to increase the drive capabilities.
In the static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.2.10 Display RAM
The display RAM is a static 40
4-bit RAM which stores LCD data. There is a one-to-one
correspondence between the RAM addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs. For details, see PCF8576D data
sheet.
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