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參數(shù)資料
| 型號(hào)： | LPC12D27FBD100/301 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 7/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT ARM CORTEX-M0 100-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | LPC1200 |
| 核心處理器： | ARM? Cortex?-M0 |
| 芯體尺寸： | 32-位 |
| 速度： | 45MHz |
| 連通性： | I²C，IrDA，SPI，SSP，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲(chǔ)器容量： | 128KB（128K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
| 其它名稱： | 568-8372 |
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LPC12D27
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 20 September 2011
15 of 46
NXP Semiconductors
LPC12D27
32-bit ARM Cortex-M0 microcontroller
7.2.2 Functional description
The PCF8576D is a versatile peripheral device interfacing the LPC1227 microcontroller
with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing
up to four backplanes and up to 40 segments.
The possible display configurations of the PCF8576D depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 4. The
integration of the LPC1227 microcontroller with the PCF8576D is shown in Figure 1.
7.2.3 Reset state of the LCD controller and pins
After power-on, the LCD controller resets to the following starting conditions:
All backplane and segment outputs are set to VLCD.
The selected drive mode is 1:4 multiplex with 1/3 bias.
Blinking is switched off.
Input and output bank selectors are reset.
The I2C-bus interface is initialized.
The data pointer and the subaddress counter are cleared (set to logic 0).
The display is disabled.
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the
reset action to complete.
7.2.4 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between VLCD and VSS(LCD). The middle resistor
can be bypassed to provide a 1/2 bias voltage level for the 1:2 multiplex configuration. The
LCD voltage can be temperature compensated externally using the supply to pin VLCD.
7.2.5 Oscillator
7.2.5.1
Internal clock
The internal logic of the PCF8576D and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin VSS(LCD). If the internal oscillator is used, the output from pin CLK can be
used as the clock signal for several PCF8576Ds in the system that are connected in
cascade.
Table 4.
Selection of display configurations
Number of
Digits/Characters
Backplanes
Segments
7-segment
14-segment
Dot matrix/Elements
4
160
20
10
160 (4
40)
3
120
15
7
120 (3
40)
2
80
10
5
64 (2
40)
140
5240 (1
40)
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