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參數(shù)資料
| 型號： | LP62S2048AM-55LLT |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 256K × 8位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 7/17頁 |
| 文件大小： | 190K |
| 代理商： | LP62S2048AM-55LLT |
LP62S2048A-T Series
PRELIMINARY
(June, 2002, Version 0.0)
7
AMIC Technology, Inc.
AC Characteristics
(T
A
= -25
°
C to + 85
°
C, VCC = 2.7V to 3.3V)
Symbol
Parameter
LP62S2048A-55LLT
LP62S2048A-70LLT
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
55
-
70
-
ns
t
AA
Address Access Time
-
55
-
70
ns
t
ACE1
Chip Enable Access Time
CE1
-
55
-
70
ns
t
ACE2
CE2
-
55
-
70
ns
t
OE
Output Enable to Output Valid
-
25
-
35
ns
t
CLZ1
Chip Enable to Output in Low Z
CE1
10
-
10
-
ns
t
CLZ2
CE2
10
-
10
-
ns
t
OLZ
Output Enable to Output in Low Z
5
-
5
-
ns
t
CHZ1
Chip Disable to Output in High Z
CE1
0
20
0
25
ns
t
CE2
0
20
0
25
ns
t
OHZ
Output Disable to Output in High Z
0
20
0
25
ns
t
OH
Output Hold from Address Change
5
-
10
-
ns
Write Cycle
t
WC
Write Cycle Time
55
-
70
-
ns
t
CW
Chip Enable to End of Write
50
-
60
-
ns
t
AS
Address Setup Time
0
-
0
-
ns
t
AW
Address Valid to End of Write
50
-
60
-
ns
t
WP
Write Pulse Width
40
-
50
-
ns
t
WR
Write Recovery Time
0
-
0
-
ns
t
WHZ
Write to Output in High Z
0
25
0
25
ns
t
DW
Data to Write Time Overlap
25
-
30
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
ns
t
OW
Output Active from End of Write
5
-
5
-
ns
Notes: t
CHZ1
, t
CHZ2
, t
OHZ
, and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP62S2048AM-70LLI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048AM-70LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048A-T | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048AU-55LLI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S2048AU-55LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM |
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