參數資料
型號: LP62S2048AM-55LLT
廠商: AMIC Technology Corporation
英文描述: 256K X 8 BIT LOW VOLTAGE CMOS SRAM
中文描述: 256K × 8位低電壓CMOS的SRAM
文件頁數: 2/17頁
文件大小: 190K
代理商: LP62S2048AM-55LLT
LP62S2048A-T Series
Preliminary
256K X 8 BIT LOW VOLTAGE CMOS SRAM
PRELIMINARY
(June, 2002, Version 0.0)
2
AMIC Technology, Inc.
Features
General Description
n
Power supply range: 2.7V to 3.3V
n
Access times: 55/70 ns (max.)
n
Current:
Very low power version: Operating: 55ns: 25mA (max.)
Standby: 10
μ
A (max.)
n
Full static operation, no clock or refreshing required
n
All inputs and outputs are directly TTL-compatible
n
Common I/O using three-state output
n
Output enable and two chip enable inputs for easy
application
n
Data retention voltage: 2V (min.)
n
Available in 32-pin SOP, TSOP, TSSOP (8X13.4mm)
and 36-pin CSP packages
70ns: 20mA (max.)
The LP62S2048A-T is a low operating current 2,097,152-bit
static random access memory organized as 262,144 words
by 8 bits and operates on a low power supply range: 2.7V to
3.3V. It is built using AMIC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included for
easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Product Family
Power Dissipation
Standby
(I
SB1
, Typ.)
Product Family
Operating
Temperature
VCC
Range
Speed
Data Retention
(I
CCDR
, Typ.)
Operating
(I
CC2
, Typ.)
Package
Type
LP62S2048A
-25
°
C ~ +85
°
C
2.7V~3.3V
55ns / 70ns
0.5
μ
A
0.5
μ
A
3mA
32L SOP
32L TSOP
32L TSSOP
36L CSP
1. Typical values are measured at VCC = 3.0V, T
A
= 25
°
C and not 100% tested.
2. Data retention current VCC = 2.0V.
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