參數(shù)資料
型號: LP62S2048AM-55LLT
廠商: AMIC Technology Corporation
英文描述: 256K X 8 BIT LOW VOLTAGE CMOS SRAM
中文描述: 256K × 8位低電壓CMOS的SRAM
文件頁數(shù): 3/17頁
文件大?。?/td> 190K
代理商: LP62S2048AM-55LLT
LP62S2048A-T Series
PRELIMINARY
(June, 2002, Version 0.0)
3
AMIC Technology, Inc.
Pin Configurations
n
SOP
n
TSOP/(TSSOP)
n
CSP (Chip Size Package)
36-pin Top View
Block Diagram
ROW
DECODER
1024 X 2048
MEMORY ARRAY
INPUT DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
CE2
CE1
OE
WE
I/O
8
I/O
1
A17
A16
A15
A0
VCC
GND
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
GND
I/O
5
I/O
6
I/O
7
I/O
8
A10
A9
A8
A13
CE2
A15
VCC
A11
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OE
L
(
1
16
17
32
Pin No.
Pin
Name
Pin No.
Pin
Name
1
2
A9
3
4
5
6
7
8
9
10
11
12
13
14
30
29
28
27
26
25
24
22
19
21
20
23
18
17
A8
A13
CE2
A15
VCC
A17
I/O
8
A16
A14
A12
A7
A6
A3
A2
A1
A0
I/O
1
I/O
2
GND
I/O
4
I/O
5
I/O
6
I/O
7
I/O
3
A11
WE
CE1
15
16
31
32
A5
A4
A10
OE
CE1
WE
A0
I/O
5
I/O
6
GND
VCC
I/O
7
I/O
8
A9
A10
OE
A11
CE1
A12
A13
A14
A16
NC
A17
A15
I/O
4
I/O
3
I/O
2
I/O
1
GND
VCC
A1
A2
CE2
WE
NC
A5
A4
A3
A6
A7
A8
6
5
4
3
2
1
A
B
C
D
E
F
G
H
相關(guān)PDF資料
PDF描述
LP62S2048M-10LLT 256K X 8 BIT LOW VOLTAGE CMOS SRAM
LP8340CLD-3.3 Low Dropout, Low IQ, 1.0A CMOS Linear Regulator
LP8340IDT-1.8 Low Dropout, Low IQ, 1.0A CMOS Linear Regulator
LP8340IDT-2.5 Low Dropout, Low IQ, 1.0A CMOS Linear Regulator
LP8340IDT-3.3 Low Dropout, Low IQ, 1.0A CMOS Linear Regulator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LP62S2048AM-70LLI 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM
LP62S2048AM-70LLT 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM
LP62S2048A-T 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM
LP62S2048AU-55LLI 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM
LP62S2048AU-55LLT 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 8 BIT LOW VOLTAGE CMOS SRAM