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參數(shù)資料
| 型號： | LMX2531LQ1500EX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.8 MM, LCC-36 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 458K |
| 代理商： | LMX2531LQ1500EX |
2.4 REGISTER R3
2.4.1 DEN[21:12] -- Extension for the Fractional Denominator
These are the MSB bits of the DEN word, which have already been discussed.
2.4.2 FoLD[3:0] -- Multiplexed Output for Ftest/LD Pin
The FoLD[3:0] word is used to program the output of the Ftest/LD Pin. This pin can be used for a general purpose I/O pin, a lock
detect pin, and for diagnostic purposes. When programmed to the digital lock detect state, the output of the Ftest/LD pin will be
high when the part is in lock, and low otherwise. Lock is determined by comparing the input phases to the phase detector. The
analog lock detect modes put out a high signal with very fast negative pulses, that correspond to when the charge pump comes
on. This output can be low pass filtered with an RC filter in order to determine the lock detect state. If the open drain state is used,
a pull-up resistor that is much larger than the resistance in the RC filter, to increase the sensitivity of the circuit. For diagnostic
purposes, the options that allow one to view the output of the R counter or the N counter can be very useful. Be aware that the
output voltage level of the Ftest/LD is not equal to the supply voltage of the part, but rather is given by V
OH and VOL in the electrical
characteristics specification.
FoLD
Output Type
Function
0
High Impedance
Disabled
1
Push-Pull
Logical High State
2
Push-Pull
Logical Low State
3
Push-Pull
Digital Lock Detect
4
N/A
Reserved
5
Push-Pull
N Counter Output Divided by 2
6
Open-Drain
Analog Lock Detect
7
Push-Pull
Analog Lock Detect
8
N/A
Reserved
9
N/A
Reserved
10
N/A
Reserved
11
N/A
Reserved
12
N/A
Reserved
13
N/A
Reserved
14
Push-Pull
R Counter Output
15
N/A
Reserved
2.4.3 ORDER -- Order of Delta Sigma Modulator
This bit determines the order of the delta sigma modulator in the PLL. In general, higher order fractional modulators tend to reduce
the primary fractional spurs that occur at increments of the channel spacing, but can also create spurs that are at a fraction of the
channel spacing, if there is not sufficient filtering. The optimal choice of modulator order is very application specific, however, a
third order modulator is a good starting point if not sure what to try first.
ORDER
Delta Sigma Modulator Order
0
Fourth
1
Reset Modulator
(Integer Mode - all fractions are ignored)
2
Second
3
Third
www.national.com
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LMX2531LQ1500E
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