參數(shù)資料
型號: LMX2531LQ1500EX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36
封裝: 6 X 6 MM, 0.8 MM, LCC-36
文件頁數(shù): 3/24頁
文件大?。?/td> 458K
代理商: LMX2531LQ1500EX
2.02 Initialization Sequence
The initial loading sequence from a cold start is described below. The registers must be program in order shown.
REGISTE
R
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
C3 C2 C1 C0
R5
INIT1
1
0
1
0
1
0
1
R5
INIT2
1
0
1
0
1
R5
1
0
1
0
1
0
1
R12
0
1
0
1
0
1
0
1
0
R9
See individual section for R9 programming information.
1
0
1
R8
See individual section for Register R8 programming information.
Register R8 only needs to be programmed for a few options of the LMX2531LQ1500E and
and only in the case that the OSCin frequency is greater than 40 MHz.
1
0
R7
See individual section for Register R7 programming information.
0
1
R6
See individual section for Register R6 programming information.
0
1
0
R4
See individual section for Register R4 programming information.
Register R4 only needs to be programmed if FastLock is used.
0
1
0
R3
See individual section for Register R3 programming information.
0
1
R2
See individual section for Register R2 programming information.
0
1
0
R1
See individual section for Register R1 programming information.
0
1
R0
See individual section for Register R0 programming information.
0
Note: There must be a minimum of 10 mS between the time when R5 is last loaded and when R1 is loaded to ensure time for the
LDOs to power up properly.
11
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LMX2531LQ1500E
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