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參數(shù)資料
| 型號： | LMX2531LQ1500EX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.8 MM, LCC-36 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 458K |
| 代理商： | LMX2531LQ1500EX |
2.3 REGISTER R2
2.3.1 R[5:0] -- R Counter Value
These bits determine the phase detector frequency. The OSCin frequency is divided by this R counter value. Note that only the
values of 1, 2, 4, 8, 16, and 32 are allowed.
R Value
Fractional
Denominator
Restrictions
R[5:0]
0,3,5-7,
9-15,17-31,
33-63
n/a
These values are illegal.
1
none
0
1
2
none
0
1
0
4
none
0
1
0
8
none
0
1
0
16
Must be
divisible by 2
0
1
0
32
Must be
divisible by 4
1
0
Note that the R counter value can put some restrictions on the fractional denominator. In the case that it is 16, the fractional
denominator must be divisible by 2, which is equivalent to saying that the LSB of the fractional denominator word is zero. In the
case that the R counter is 32, the two LSB bits of the fractional denominator word must also be zero, which is equivalent to saying
that the fractional denominator must be divisible by 4. Because the fractional denominator can be very large, this should cause no
issues. For instance, if one wanted to achieve a fractional word of 1/65, and the R counter value was 16, the fractional word could
be changed t0 4/260 ,and the same resolution could be achieved.
2.3.2 DEN[21:12] and DEN[11:0]-- Fractional Denominator
These bits determine the fractional denominator. Note that the MSB bits for this word are in register R3. If the FDM bit is set to 0,
DEN[21:12] are ignored. The fractional denominator should only be set to zero if the fractional circuitry is being disabled by setting
ORDER=1. A value of one never makes sense to use. All other values could reasonably be used in fractional mode.
DEN[21:12]
DEN[11:0]
Fra
ctio
nal
Den
omi
nat
or
0
...
409
5
1
409
6
0
1
0
...
419
430
3
1
15
www.national.com
LMX2531LQ1500E
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