參數(shù)資料
型號(hào)： LMX2531LQ1500EX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36
封裝： 6 X 6 MM, 0.8 MM, LCC-36
文件頁(yè)數(shù)： 22/24頁(yè)
文件大?。?/td> 458K
代理商： LMX2531LQ1500EX
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout)
V
IH
High-Level Input Voltage
1.6
2.75
V
IL
Low-Level Input Voltage
0.4
V
I
IH
High-Level Input Current
V
IH = 1.75
-3.0
3.0
A
I
IL
Low-Level Input Current
V
IL = 0 V
-3.0
3.0
A
V
OH
High-Level Output Voltage
I
OH = 500 A
2.0
2.65
V
OL
Low-Level Output Voltage
I
OL = -500 A
0.0
0.4
V
MICROWIRE Timing
t
CS
Data to Clock Set Up Time
See Data Input Timing
25
ns
t
CH
Data to Clock Hold Time
See Data Input Timing
20
ns
t
CWH
Clock Pulse Width High
See Data Input Timing
25
ns
t
CWL
Clock Pulse Width Low
See Data Input Timing
25
ns
t
ES
Clock to Enable Set Up Time
See Data Input Timing
25
ns
t
CES
Enable to Clock Set Up Time
See Data Input Timing
25
ns
t
EWH
Enable Pulse Width High
See Data Input Timing
25
ns
Note 2:
Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(Fcomp) where L(f) is defined as the single side band phase noise
measured at an offset frequency, f, in a 1 Hz Bandwidth and Fcomp is the comparison frequency of the synthesizer. The offset frequency, f, must be chosen
sufficiently smaller then the loop bandwidth of the PLL, and large enough to avoid a substantial noise contribution from the reference.
Note 3:
Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency
calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for
continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the part was initially programmed
at, the temperature can never drift outside the frequency range of -40°C
≤T
A≤ 85°C without violating specifications.
Note 4:
The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The maximum limits apply
only at center frequency and over temperature, assuming that the part is reloaded at each test frequency. Over frequency, the phase noise can vary 1-2 dB, with
the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies 1-2 dB, assuming the part is reloaded.
Serial Data Timing Diagram
20195003
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is
sent from the shift registers to an actual counter. A slew rate of at least 30 V/s is recommended for these signals. After the
programming is complete, the CLK, DATA, and LE signals should be returned to a low state. If the CLK and DATA lines are toggled
while the in VCO is in lock , as is sometimes the case when these lines are shared with other parts, the phase noise may be
degraded during the time of this programming.
7
www.national.com
LMX2531LQ1500E
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