參數(shù)資料
型號(hào)： LMX2364TMX/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 2600 MHz, PDSO24
封裝： TSSOP-24
文件頁(yè)數(shù)： 31/39頁(yè)
文件大?。?/td> 694K
代理商： LMX2364TMX/NOPB
Supplemental Information (Continued)
3.5 RF PLL FASTLOCK REFERENCE TABLE
The table below shows most of the trade offs involved in
choosing a steady-state charge pump current (RF_CP), the
FastLock charge pump current (RF_CPF[1:0]), and the
Cycle Slip Reduction Factor CSR.
Parameter
Advantages to Choosing Smaller
Advantages to Choosing Larger
RF_CP
1. Allows capacitors in loop filter to be smaller
values making it easier to find physically
smaller components and components with
better dielectric properties.
Phase noise, especially within the loop
bandwidth of the system will be slightly worse
for lower charge pump currents. If the charge
pump gain is at least 4 mA, most of the
phase noise benefit will be realized.
2. Allows a larger loop bandwidth multiplier for
FastLock, or a higher cycle slip reduction
factor.
RF_CPF
The only reason not to always choose this to
16 mA is to make it such that no FastLock
resistor is required for FastLock. For 3rd and
4th order filters, it is not possible to keep the
filter perfectly optimized by simply switching in
a resistor for FastLock.
This allows the maximum possible benefit for
FastLock.
RF_CSR
Do not choose this any larger than necessary
to eliminate cycle slipping. Keeping this small
allows a larger loop bandwidth multiplier for
FastLock.
This will eliminate cycle slips better.
3.6 CAPACITOR DIELECTRIC CONSIDERATIONS
The LMX2364 has a high fractional modulus and high
charge pump gain for the lowest possible phase noise. One
consideration is that the reduced N value and higher charge
pump may cause the capacitors in the loop filter to become
larger in value. For larger capacitor values, it is common to
have a trade-off between capacitor dielectric quality and
physical size. Using film capacitors or NP0/CG0 capacitors
yields the best possible lock times, where as using X7R or
Z5R capacitors can increase lock time by 0 – 500%. In
general, designs with higher comparison frequencies tend to
be less succeptible to degradations in lock time due to
capacitor dielectric effects. Capacitor dielectrics have very
little impact on phase noise or spurs. Although the use of
lesser quality dielectric capacitors may be unavoidable in
many circumstances, allowing a larger footprint for the loop
filter capacitors, using a lower charge pump current, and
reducing the fractional modulus are all ways to reduce ca-
pacitor values.
LMX2364
www.national.com
37
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