= 0.00164,
MHz
V
(2.03 - 0.814) 10
6
12.288 81.4 - (-81.4)
(
)
'V 10
6
FNOM ('ppm2 - 'ppm1)
KVCO =
= 0.00164
MHz
V
2.03 - 0.814
0.001 - (-0.001)
KVCO =
'F
'V
,
MHz
V
=
¨
§ 'F
2 - 'F1
VTUNE2 - VTUNE1
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
The tuning curve achieved in the user's application may differ from the curve shown above due to differences in
PCB layout and component selection.
This data is measured on the bench with the crystal integrated with the LMK04000 family. Using a voltmeter to
monitor the VTUNE node for the crystal, the PLL1 reference clock input frequency is swept in frequency and the
resulting tuning voltage generated by PLL1 is measured at each frequency. At each value of the reference clock
frequency, the lock state of PLL1 should be monitored to ensure that the tuning voltage applied to the crystal is
valid.
The curve shows over the tuning voltage range of 0.17 VDC to 3.0 VDC, the frequency range is ± 163 ppm; or
equivalently, a crystal frequency range of ± 2000 Hz. The measured tuning voltage at the nominal crystal
frequency (12.288 MHz) is 1.4 V. Using the diode data sheet tuning characteristics, this voltage results in a
tuning capacitance of approximately 6.5 pF.
The tuning curve data can be used to calculate the gain of the oscillator (KVCO). The data used in the calculations
is taken from the most linear portion of the curve, a region centered on the crossover point at the nominal
frequency (12.288 MHz). For a well designed circuit, this is the most likely operating range. In this case, the
tuning range used for the calculations is ± 1000 Hz (± 0.001 MHz), or ± 81.4 ppm. The simplest method is to
calculate the ratio:
ΔF2 and ΔF1 are in units of MHz. Using data from the curve this becomes:
A second method uses the tuning data in units of ppm:
FNOM is the nominal frequency of the crystal and is in units of MHz. Using the data, this becomes:
In order to ensure startup of the oscillator circuit, the equivalent series resistance (ESR) of the selected crystal
crystal with adequate power dissipation capability, or drive level. If the drive level supplied by the oscillator
exceeds the maximum specified by the crystal manufacturer, the crystal will undergo excessive aging and
possibly become damaged. Drive level is directly proportional to resonant frequency, capacitive load seen by the
crystal, voltage and equivalent series resistance (ESR). For more complete coverage of crystal oscillator design,
see
Application
Note
AN-1939
at
or
Termination and use of Clock Output (Drivers)
When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:
Transmission line theory should be followed for good impedance matching to prevent reflections.
Clock drivers should be presented with the proper loads. For example:
–
LVDS drivers are current drivers and require a closed current loop.
–
LVPECL drivers are open emitters and require a DC path to ground.
Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage)
for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage
level. In this case, the signal should normally be AC coupled.
Copyright 2008–2011, Texas Instruments Incorporated
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