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| 型號(hào)： | LMK04033BEVAL |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 19/65頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR LMK04033BISQ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘調(diào)節(jié)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LMK04033 |
| 主要屬性： | 122.88 MHz VCXO |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板，線纜，文檔 |
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SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
The Phase Frequency Detector in PLL2 then compares the divided (R Divider 2) reference signal from the PLL2
OSCin port with the divided (N Divider 2 and VCO Divider) output of the internal VCO. The bandwidth of the
external loop filter for PLL2 should be designed to be wide enough to take advantage of the low in-band phase
noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is passed through a
common VCO divider block and placed on a distribution path for the clock distribution section. It is also routed to
the PLL2_N counter. Each clock output channel allows the user to select a path with a programmable divider
block, a phase synchronization circuit, a programmable delay, and LVDS/LVPECL/2VPECL/LVCMOS compatible
output buffers.
Phase Detector 1 (PD1)
Phase Detector 1 in PLL1 (PD1) can operate up to 40 MHz. Since a narrow loop bandwidth should be used for
PLL1, the need to operate at high phase detector rate to lower the in-band phase noise becomes unnecessary.
Phase Detector 2 (PD2)
Phase Detector 2 in PLL2 (PD2) supports a maximum comparison rate of 100 MHz, though the actual maximum
frequency at the input port (PLL2 OSCin/OSCin*) is 250 MHz. Operating at highest possible phase detector rate
will ensure low in-band phase noise for PLL2 which in turn produces lower total jitter, as the in-band phase noise
from the reference input and PLL are proportional to N2.
PLL2 Frequency Doubler
The PLL2 reference input at the OSCin port may be optionally routed through a frequency doubler function rather
than through the PLL2_R counter. The maximum phase comparison frequency of the PLL2 phase detector is 100
MHz, so the input to the frequency doubler is limited to a maximum of 50 MHz. The frequency doubler feature
allows the phase comparison frequency to be increased when a relative low frequency oscillator is driving the
OSCin port. By doubling the PLL2 phase comparison frequency, the in-band PLL2 noise is reduced by about 3
dB.
Inputs / Outputs
PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*)
The reference clock inputs for PLL1 may be selected from either CLKin0 and CLKin1. The user has the capability
to manually select one of the two inputs or to configure an automatic switching mode operation. A detailed
description of this function is described in the uWire programming section of this data sheet.
PLL2 OSCin / OSCin* Port
The feedback from the external oscillator being locked with PLL1 is injected to the PLL2 OSCin/OSCin* pins.
This input may be driven with either a single- ended or differential signal. If operated in single ended mode, the
unused input should be tied to GND with a 0.1 F capacitor. Either AC or DC coupling is acceptable. Internal to
the chip, this signal is routed to the PLL1_N Counter and to the reference input for PLL2. The internal circuitry of
the OSCin port also supports the optional implementation of a crystal based oscillator circuit. A crystal, varactor
diode and a small number of other external components may be used to implement the oscillator. The internal
oscillator circuit is enabled by setting the EN_PLL2_XTAL bit.
CPout1 / CPout2
The CPout1 pin provides the charge pump current output to drive the loop filter for PLL1. This loop filter should
be configured so that the total loop bandwidth for PLL1 is less than 200 Hz. When combined with an external
oscillator that has low phase noise at offsets close to the carrier, PLL1 generates a reference for PLL2 that is
frequency locked to the PLL1 reference clock but has the phase noise performance of the oscillator. The CPout2
pin provides the charge pump current output to drive the loop filter for PLL2. This loop filter should be configured
so that the total loop bandwidth for PLL2 is in the range of 50 kHz to 200 kHz. See the section on uWire device
control for a description of the charge pump current gain control.
26
Copyright 2008–2011, Texas Instruments Incorporated
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMK04033BEVAL/NOPB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 LMK04033BISQ EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| LMK04033BISQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04033BISQ/NOPB | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LMK04033BISQE | 制造商:Texas Instruments 功能描述:Clock Conditioner 48-Pin LLP EP T/R 制造商:Texas Instruments 功能描述:PRECISION CLOCK CONDITIONER, 48LLP |
| LMK04033BISQE/NOPB | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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