參數(shù)資料
型號: LMK04031BEVAL/NOPB
廠商: National Semiconductor
文件頁數(shù): 27/65頁
文件大小: 0K
描述: EVAL BOARD LMK04031BISQ
標準包裝: 1
系列: PowerWise®
主要目的: 計時,多用途
嵌入式:
已用 IC / 零件: LMK04031
已供物品: 板,線纜,文檔,軟件
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
CLKoutX_DLY: Clock Channel Phase Delay Adjustment
Each output channel has an output delay register that can be used to introduce a lag relative to the distribution
path frequency (VCO Divider output). These registers support a 150 ps stepsize and range from 0 to 2.25 ns of
total delay. When the channel phase delay registers are enabled, a nominal fixed delay of 300 ps of delay is
incurred in addition to the programmed delay. The Channel Phase Delay Adjustment Registers are 4 bits wide
and are programmed as follows:
Table 7. CLKoutX_DLY: Clock Channel Delay Control Bit Values
CLKoutX_DLY [ 3:0 ]
DELAY (ps)
b3
b2
b1
b0
0
1
150
0
1
0
300
0
1
450
0
1
0
600
0
1
0
1
750
0
1
0
900
0
1
1050
1
0
1200
1
0
1
1350
1
0
1
0
1500
1
0
1
1650
1
0
1800
1
0
1
1950
1
0
2100
1
2250
CLKoutX/CLKoutX* LVCMOS Mode Control
For clock outputs that are configured as LVCMOS, the LVCMOS CLKoutX/CLKoutX* outputs can be
independently configured by uWire CLKoutXA_STATE and CLKoutXB_STATE bits. The following choices are
available for LVCMOS outputs:
Table 8. CLKoutXA_STATE, CLKoutXB_STATE Control Bits for LVCMOS Modes
CLKoutXA_STATE
CLKoutXB_STATE
LVCMOS Modes
b1
b0
b1
b0
0
Inverted
0
1
0
1
Normal
1
0
1
0
Low
1
TRI-STATE
CLKoutX/CLKoutX* LVPECL Mode Control
Clock outputs designated as LVPECL can be configured in one of two possible output levels. The default mode
is the common LVPECL swing of 800 mVp-p single-ended (1.6 Vp-p differential). A second mode, 2VPECL, can
be enabled in which the swing is increased to 1000 mVp-p single-ended (2 Vp-p differential).
Table 9. LVPECL Output Format Control
CLKoutX_PECL_LVL
Output Format
0
LVPECL (800 mVpp)
1
2VPECL (1000 mVpp)
Copyright 2008–2011, Texas Instruments Incorporated
33
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