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參數(shù)資料
| 型號： | LM9811 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor |
| 中文描述： | 10位Greyscale/30-Bit彩色線陣CCD傳感器處理器 |
| 文件頁數(shù)： | 32/36頁 |
| 文件大?。?/td> | 605K |
| 代理商： | LM9811 |
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Applications Information
(Continued)
RS Pulse Polarity = 0 (or 1 if circuit of Figure 40 is used)
*
RS Pulse Position = 0
Sample Reference Position = 2
Sample Signal Position = 14
φ
1/
φ
2/RS/TR Enable = 0/0/1/1
TR Pulse Width = 0
TR-
φ
1 Guardband = 0
TR Polarity = 1
*
Signal Polarity = 0
Dummy Pixels = 2
Optical Black Pixels = 10
(
*
Value given in CCD datasheet)
As CIS sensors approach pixel rates of 1MHz and above
(corresponding to MCLK frequencies of 8MHz and above),
the voltage during the reset level becomes less stable, mak-
ing it difficult to perform CDS on the output (Figure 41). The
solution is to create the ground reference externally, shorting
the LM9811’s input to ground for half of the time using the
φ
1
clock, as shown in Figure 42
10.0 HINTS AND COMMON SYSTEM DESIGN
PROBLEMS
10.1 Reading and Writing to the Configuration Register
The Configuration Register sends and receives data LSB
(Least Significant Byte) first. Some microcontrollers send out
data MSB (Most Significant Byte) first. The order of the bits
must be reversed to when using these microcontrollers.
Note:
Unlike the LM9800, the SYNC pin does not have to be held high to
send or receive data to or from the Configuration Register.
10.2 Setting the Dummy and Optical Black Pixel
Registers
The minimum value in the Dummy Pixels register is 2 (a
value of 0 or 1 will cause errors in the EOC and CCLK tim-
ing). Note that the value in this register should be equal to 1
plus the actual number of dummy pixels in the CCD. For ex-
ample, if the CCD being used with the LM9811 has 12
dummy pixels, this register should be set to 13. The mini-
mum number in the Optical Black Pixels register is 1.
10.3 Stretching the TR-
φ
1 Guardband
Some CCDs (Sony’s ILX514, ILX518, and ILX524, for ex-
ample) require a TR to
φ
1 guardband greater than the 167ns
(2 MCLKs) provided by the LM9811. The circuit shown in
Figure 43 produces a 1 μs
φ
ROG (transfer) pulse with a
guardband between the end of the
φ
ROG pulse and the next
edge of
φ
1. This is done by setting the LM9800’s TR pulse
width register to 2 μs and using the 74HC4538 to generate a
1 μs pulse inside that TR period to send to the CCD.
Figure 44 shows a different technique for increasing the
TR-
φ
1 guardband and/or increasing the length of the TR
pulse by stopping the MCLK during the TR period. When TR
initially goes high, the first one-shot (U1A) triggers, effec-
tively disabling the LM9811s MCLK for
≈
2 μs, thereby length-
ening the TR pulse width by
≈
2 μs over the value pro-
grammed in the configuration register. On the falling edge of
TR, the second one-shot (U1B) fires, disabling the LM9811s
MCLK for
≈
1 μs and increasing the TR-
φ
1 guardband by that
amount.
DS012813-49
FIGURE 41. High Speed CIS Waveforms
DS012813-50
FIGURE 42. High Speed CIS Interface
DS012813-51
FIGURE 43. Stretching the TR-
φ
1 Guardband
www.national.com
32
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相關(guān)代理商/技術(shù)參數(shù) |
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| LM9811CCV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor |
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| LM981-SC36 | 功能描述:基本/快動開關(guān) Foot Switch RoHS:否 制造商:Omron Electronics 觸點形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級:IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
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