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參數(shù)資料
| 型號： | LM9811 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor |
| 中文描述： | 10位Greyscale/30-Bit彩色線陣CCD傳感器處理器 |
| 文件頁數(shù)： | 30/36頁 |
| 文件大?。?/td> | 605K |
| 代理商： | LM9811 |
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Applications Information
(Continued)
8.0 TYPICAL GREYSCALE APPLICATION
Figure 34 shows the interface between the LM9811 and a
typical greyscale even/odd output CCD, the TCD1250. The
interface for most other CCDs will be similar, the only differ-
ence being the values for the series resistors (if required).
The clamp capacitor value is determined as shown in Sec-
tion 4.2. The resistor values are usually given in the CCD’s
datasheet. If the datasheet’s requirement is given as a par-
ticular rise/fall time, the resistor can be chosen using the
graph of
φ
1,
φ
2, RS and TR Rise Times Through A Series
Resistance vs Load Capacitance
graph in the
Typical Per-
formance Characteristics
section. Given the required rise
time and the input capacitance of the input being driven, the
resistor value can be estimated from the graph.
These are the Configuration Register parameters recom-
mended for use as a starting point for most even/odd CCDs:
Mode = 1 (Even/Odd mode)
*
RS Pulse Width = 0 (1 MCLK),
RS Pulse Polarity = 0
*
RS Pulse Position = 10,
Sample Reference Position = 14,
Sample Signal Position = 8,
φ
1/
φ
2/RS/TR Enable = 1/1/1/1
TR Pulse Width = 0
TR-
φ
1 Guardband = 0
TR Polarity = 0
*
Signal Polarity = 1
Dummy Pixels = 2
*
Optical Black Pixels = 5
*
(
*
Value given in CCD datasheet)
The Mode is set to Even/Odd, RS Pulse Width is set to its
minimum value, and RS polarity is positive. The timing,
shown in Figure 35 is determined by the RS, SR, and SS
registers. The RS pulse position (RS) is set to 10, dividing
the pixel period so that the signal portion is available for the
first 5 MCLKs following a
φ
1 clock edge and the black refer-
ence portion appears during the last 2 MCLKs (following the
1 MCLK wide reset pulse). Sample Reference (SR) is set to
14, so it samples the black reference just before the next
φ
1
clock edge. Sample Signal (SS) is set to 8, so it samples the
black reference just before the next reset pulse. These val-
ues can be adjusted to account for differences in CCDs,
CCD data delays, settling time, etc., but this is often not
necessary.
All 4 digital outputs (
φ
1,
φ
2, RS, and TR) are enabled. The
TR pulse width is set to the minimum, 20 MCLKs, as is the
guardband between
φ
1 and TR. Either of these settings can
be increased if necessary.
The TR polarity is positive, as is the RS polarity. Some CCDs
may require one or both of these signals to be inverted, in
which case the corresponding bit can be set to a “1”. If there
is an inverting buffer between the LM9811 and the CCD,
these bits may be used to correct the output polarity at the
CCD. Note that if
φ
1 and
φ
2 are inverted, then
φ
2 should be
used as
φ
1 at the CCD, and
φ
1 should be used as
φ
2 at the
CCD (Figure 36 ).
DS012813-41
FIGURE 33. Parallel Output CCD, Three LM9811
DS012813-42
FIGURE 34. Greyscale CCD Interface Example
DS012813-43
FIGURE 35. Typical Even/Odd Timing
DS012813-44
FIGURE 36.
φ
1 and
φ
2 After Inversion
www.national.com
30
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相關代理商/技術參數(shù) |
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| LM981-SC36 | 功能描述:基本/快動開關 Foot Switch RoHS:否 制造商:Omron Electronics 觸點形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級:IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
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