參數(shù)資料
型號: LM9811
廠商: National Semiconductor Corporation
英文描述: 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor
中文描述: 10位Greyscale/30-Bit彩色線陣CCD傳感器處理器
文件頁數(shù): 24/36頁
文件大?。?/td> 605K
代理商: LM9811
Applications Information
(Continued)
The final value for C
should be less than or equal to
C
, but no less than C
CLAMP MIN
. A value of 470 pF
will work in this example.
In some cases, depending on primarily on the choice of
CCD, C
may actually be lessthan the C
,
meaning that the capacitor cannot be charged to its final volt-
age during the black pixels at the beginning of a line and hold
its voltage without drooping for the duration of that line. This
is usually not a problem because in most applications the
CCD is clocked continuously as soon as power is applied. In
this case, a larger capacitor can be used (guaranteeing that
the C
requirement is met), and the final clamp volt-
age is forced across the capacitor over multiple lines. This is
the equation to calculate how many lines are required before
the capacitor settles to the desired accuracy:
Using the values shown before and a clamp capacitor value
of 0.01 μF, this works out to be:
At a 2.5MHz conversion rate, this is about 14ms.
In this example a 0.01 μF capacitor takes 14ms after
power-up to charge to its final value, but its droop across all
subsequent lines is now less than 2 mV (using the previous
example’s values). This wide margin is the reason a C
CLAMP
value of 0.01 μF will work in most applications.
4.3 VGA
The LM9811 has a VGA(Variable GainAmplifier) that can be
used to increase the amplitude of the CCD signal prior to
sampling, correction, and digitization. The gain of the VGA is
0 dB to 9 dB and is determined by the codes in the 4-bit VGA
Gain register, as given by the equation:
This gain may be changed at the line rate (not the pixel rate)
by writing to the configuration register. You can write to the
configuration register to change the gain at any time, but if
you write during a line, the remaining pixels of that line may
be corrupted. It is best to change the gain after all active pix-
els have been read out or while SYNC is low.
4.4 Correlated Double Sampler (CDS)
Figure 23 shows the output stage of a typical CCD and the
resulting output waveform:
Capacitor C1 converts the electrons coming from the CCD’s
shift register to an analog voltage. The source follower out-
put stage (Q2) buffers this voltage before it leaves the CCD.
Q1 resets the voltage across capacitor C1 in between every
pixel at intervals 2 and 5. When Q1 is on, the output signal
(OS) is at its maximum. After Q1 turns off (period 3), the OS
level represents the residual voltage across C1 (V
).
V
includes charge injection from Q1, thermal noise
from the ON resistance of Q1, and other sources of error.
When the shift register clock (
φ
1) makes a low to high tran-
sition (period 4), the electrons from the next pixel flow into
C1. The charge across C1 now contains the voltage propor-
tional to the number of electrons plus V
, an error
term. If OS is sampled at the end of period 3 and that voltage
is subtracted from the OS at the end of period 4, the
V
term is canceled and the noise on the signal is re-
duced. ([V
+V
] V
= V
SIGNAL
). This
is the principal of Correlated Double Sampling.
The LM9811 implements CDS with two switched-capacitor
S/H amplifiers. With a 12MHz MCLK input, the LM9811’s
S/Hs acquire a signal within an 83ns window which can be
placed anywhere in the pixel period with 42ns precision. See
Figures 7, 8 for more detailed timing information.
4.5 CIS Mode
The LM9811 provides some support for CIS (Contact Image
Sensor) devices by offering a sampling mode for capturing
positive going signals, as opposed to the CCD’s negative go-
ing signal.
DS012813-31
FIGURE 23. CDS
www.national.com
24
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