參數(shù)資料
型號(hào)： LM12434CIWMX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： SOP-28
文件頁(yè)數(shù)： 56/80頁(yè)
文件大?。?/td> 1552K
代理商： LM12434CIWMX
20 Electrical Specifications (Continued)
221 Converter Static Characteristics
The following specifications apply to the LM12434 and LM12 L 438 for VAa e
VDa e 5V 33V AGND e DGND e 0V VREFa e 4096V 25V VREFb e 0V 12-bit a sign conversion mode fCLK e
80 MHz
6 MHz
RS e 25X source impedance for VREFa and VREFb s 25X fully-differential input with fixed 2048V
125V common-mode voltage and minimum acquisition time unless otherwise specified Boldface limits apply for TA e
TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 7 8 and 9) (Continued)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 10)
(Note 11)
(Limit)
DNL
8-Bit a Sign and ‘‘Watchdog’’ Mode
g
015
g
12
LSB (max)
Differential Non-Linearity
8-Bit a Sign and ‘‘Watchdog’’ Mode
After Auto-Zero
g
005
g
12
LSB (max)
Zero Error
8-Bit a Sign and ‘‘Watchdog’’ Positive
g
01
g
12
LSB (max)
and Negative Full-Scale Error
8-Bit a Sign and ‘‘Watchdog’’ Mode
g
18
LSB
DC Common Mode Error
Multiplexer Channel-to-Channel
g
005
LSB
Matching
VINa
Non-Inverting
GND
V (min)
Input Range
VAa
V (max)
VINb
Inverting
GND
V (min)
Input Range
VAa
V (max)
VINa b VINb Differential Input Voltage Range
b
VAa
V (min)
VAa
V (max)
VINa b VINb
2
Common Mode Input Voltage Range
GND
V (min)
VAa
V (max)
PSS
Power Supply
Zero Error VAa e VDa e 5V g10%
g
005
g
10
LSB (max)
Sensitivity
Full-Scale Error VREFa e 4096V VREFb e GND
g
025
g
15
LSB (max)
(Note 15)
Linearity Error
g
02
LSB
CREF
VREFa VREFb Input Capacitance
85
pF
CIN
Selected Multiplexer Channel Input
75
pF
Capacitance
222 Converter Dynamic Characteristics
The following specifications apply only to the LM12434 and LM12438 for VAa e
VDa e 5V AGND e DGND e 0V VREFa e 4096V VREFb e 0V 12-bit a sign conversion mode fCLK e 80 MHz
throughput rate e 1333 kHz RS e 25X source impedance for VREFa and VREFb s 25X fully-differential input with fixed
2048V 125V common-mode voltage and minimum acquisition time unless otherwise specified Boldface limits apply
for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 7 8 and 9)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 10)
(Note 11)
(Limit)
CLK Duty Cycle
50
%
40
% (min)
60
% (max)
tC
Conversion Time
13-Bit Resolution
44 (tCLK)
44 (tCLK) a 50 ns
(max)
Sequencer State S5
(Figure 10)
9-Bit Resolution
21 (tCLK)
21 (tCLK) a 50 ns
(max)
Sequencer State S5
(Figure 10)
tA
Acquisition Time
Sequencer State S7
(Figure 10)
tCLK e CLK Period
(Programmable)
Minimum for 13-Bits
9 (tCLK)
9(tCLK) a 50 ns
(max)
Maximum for 13-Bits (D e 15)
39 (tCLK)
39 (tCLK) a 50 ns
(max)
Minimum for 9-Bits
(Figure 10)
2(tCLK)
2(tCLK) a 50 ns
(max)
Maximum for 9-Bits (D e 15)
2 (tCLK)
32 (tCLK) a 50 ns
(max)
6
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