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參數(shù)資料
| 型號： | LM12434CIWMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 2/80頁 |
| 文件大?。?/td> | 1552K |
| 代理商： | LM12434CIWMX |
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20 Electrical Specifications (Continued)
23 DIGITAL SWITCHING CHARACTERISTICS
The following specifications apply to the LM12434 and LM12 L 438 for VAa
e
VDae 5V 33V
AGND e DGND e 0V CL (load capacitance) on output lines e 80 pF unless otherwise specified
Boldface limits apply for TA e TJ e TMIN to TMAX all other limits for TA e TJ e 25 C (Notes 6 7 and 9)
231 Standard Mode Interface (MICROWIREPLUSTM SCI and SPIQSPI)
Symbol
Parameter
Conditions
Typical
Limits
Units
(See
Figure Below)
(Note 10)
(Note 11)
(Limit)
t1
SCLK (Serial Clock) Period
100 125
ns (min)
t2
CS Set-Up Time to First
25 30
ns (min)
Clock Transition
t3
DI Valid Set-Up Time to Data
0
ns (min)
Capture Transition of SCLK
t4
DI Valid Hold Time to Data
40
ns (min)
Capture Transition of SCLK
t5
DO Hold Time from Data Shift
70 120
ns (max)
Transition of SCLK
t6
CS Hold Time from Last SCLK
Transition in a Read or Write Cycle
25
ns (min)
(Excluding Burst Read Cycle)
t7
CS Inactive to CS Active Again
3
CLK Cycle
(min)
t8
SCLK Idle Time between the
End of the Command Byte
3
CLK Cycle
Transfer and the Start of the
(min)
Data Transfer in Read Cycles
CLK is the main clock input to the device pin number 24 in PLCC package or pin number 2 in SO package
TLH11879 – 18
10
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