參數(shù)資料
型號: LM12434CIWMX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封裝: SOP-28
文件頁數(shù): 25/80頁
文件大?。?/td> 1552K
代理商: LM12434CIWMX
60 Operational Information (Continued)
CONFIGURATION REGISTER
(ReadWrite)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Diag
Test
RAM
Sync
AZ Each
IS
Stand-
Full
Auto
Reset
Start
Pointer
IO
Cycle
by
Cal
Zero
D0
Start 0 stops the instruction execution 1 starts the instruction execution
D1
Reset When set to 1 resets Start bit also resets all the bits in status registers and resets the instruction pointer to
zero D1 will then automatically reset itself to zero after 2 clock pulses
D2
Auto-Zero When set to 1 a long (8-cycle) auto-zero calibration cycle is performed
D3
Full Calibration When set to 1 a full calibration cycle (linearity and auto-zero) is performed
D4
Standby When set to 1 the chip goes to low-power standby mode Resetting the bit will return the chip to active
mode after a short delay
D5
IS Instruction
or extended sign 0 e Bits 13 – 15 of the conversion result hold the instruction number to which the
result belongs 1 e Bits 13 – 15 of the result hold the extended sign bit
D6
AZ each Cycle When set to 1 a short auto-zero cycle is performed before each conversion
D7
Sync IO 0 e Sync pin is input 1 e Sync pin is output
D9 – D8
RAM Pointer Selects the sections of the instruction RAM 00 e Instruction 01 e Limits
1 10 e Limits
2
D10
This bit is used for production testing and must be kept zero for normal operation
D11
Diagnostic When set to 1 the LM12 L 438 will perform a diagnostic conversion along with a properly selected
instruction This mode is not available on the LM12434
D15 – D12 Don’t Care
INSTRUCTION RAM
(ReadWrite)
Instruction
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Acquisition Time
Watchdog
812
Timer
Sync
MUXINb
MUXINa
Pause
Loop
D0
Loop 0 e Go to next instruction 1 e Loop back to in instruction
0
D1
Pause 0 e No pause 1 e Pause don’t do the instruction The start bit in the Configuration register resets to 0 when
a pause encountered a 1 written to the Start bit restarts the instruction execution
MUXINa For the LM12 L 438 these bits select which input channel is connected to the ADC’s non-inverting input
For the LM12434 they select which input channel is connected to MUXOUTa
D7 – D5
MUXINb For the LM12 L 438 these bits select which input channel is connected to the ADC’s inverting input For
the LM12434 they select which input channel is connected to MUXOUTb
D8
Sync 0 e Normal operation internal timing SYNC is an output 1 e SYNC is an input SH and conversion
(comparison) timing are controlled by an external signal applied to SYNC pin
D9
Timer 0 e Timer is not used for this instruction 1 e Instruction execution does not begin until timer counts down to
zero
D10
812 0 e 12-bit a sign resolution 1 e 8-bit a sign resolution
D11
Watchdog 0 e Conventional conversion (no watchdog comparison) 1 e Instruction performs watchdog compari-
sons
D15 – D12 Acquisition Time Determines SH acquisition time
For 12-bit a sign (9a2D) clock cycles For 8-bit a sign (2 a 2D) clock cycles
Where D e Contents of D15 – D12
For 12-bit a sign Choose D for D t 045 x RS kX c fCLK MHz
For
8-bit a sign Choose D for D t 036 x RS kX c fCLK MHz
Where RS e Input source resistance
FIGURE 9 Bit Assignments for LM12434 and LM12 L 438 Internal Registers
(Continued)
31
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