參數(shù)資料
型號(hào)： LM12434CIV
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： Sign Data Acquisition System with Serial I/O and Self-Calibration
中文描述： SPECIALTY ANALOG CIRCUIT, PQCC28
封裝： PLASTIC, LCC-28
文件頁(yè)數(shù)： 36/80頁(yè)
文件大小： 1561K
代理商： LM12434CIV
6.0 Operational Information
(Continued)
6.2.2 Configuration Register
The Configuration register is a 16-bit control register with
read/write capability. It acts as the LM12434’s and
LM12
à
L
ó
438’s ‘‘control panel’’ holding global information
as well as start/stop, reset, self-calibration, and stand-by
commands.
Bit 0
is the START/STOP bit. Reading Bit 0 returns an indi-
cation of the Sequencer’s status. A ‘‘0’’ indicates that the
Sequencer is stopped and waiting to execute the next in-
struction. A ‘‘1’’ shows that the Sequencer is running. Writ-
ing a ‘‘0’’ halts the Sequencer when the current instruction
has finished execution. The next instruction to be executed
is pointed to by the instruction pointer found in the status
register. Writing a ‘‘1’’ to Bit 0 restarts the Sequencer with
the instruction currently pointed to by the instruction pointer.
(See Bits 8–10 in the Interrupt Status register.)
Bit 1
is the DAS’ system RESET bit. Writing a ‘‘1’’ to Bit 1
stops the Sequencer (resetting the Configuration register’s
START/STOP bit), resets the Instruction pointer to ‘‘000’’
(found in the Interrupt Status register), clears the Conver-
sion FIFO, and resets all interrupt flags. The RESET bit will
return to ‘‘0’’ after two clock cycles unless it is forced high
by writing a ‘‘1’’ into the Configuration register’s Standby bit.
A reset signal is internally generated when power is first
applied to the part. No operation should be started until the
RESET bit is ‘‘0’’.
Bit 2
is the auto-zero bit. Writing a ‘‘1’’ to this bit initiates an
auto-zero offset voltage calibration. Unlike the eight-sample
auto-zero calibration performed during the full calibration
procedure, Bit 2 initiates a ‘‘short’’ auto-zero by sampling
the offset once and creating a correction coefficient (full
calibration averages eight samples of the converter offset
voltage when creating a correction coefficient). If the Se-
quencer is running when Bit 2 is set to ‘‘1’’, an auto-zero
starts immediately after the conclusion of the currently run-
ning instruction. Bit 2 is reset automatically to a ‘‘0’’ and an
interrupt flag (Bit 3, in the Interrupt Status register) is set at
the end of the auto-zero (76 clock cycles). After completion
of an auto-zero calibration, the Sequencer fetches the next
instruction as pointed to by the Instruction RAM’s pointer
and resumes execution. If the Sequencer is stopped, an
auto-zero is performed immediately at the time requested.
Bit 3
is the calibration bit. Writing a ‘‘1’’ to this bit initiates a
complete calibration process that includes a ‘‘long’’ auto-
zero offset voltage correction (this calibration averages
eight samples of the comparator offset voltage when creat-
ing a correction coefficient) followed by an ADC linearity
calibration. This complete calibration is started after the cur-
rently running instruction is completed if the Sequencer is
running when Bit 3 is set to ‘‘1’’. Bit 3 is reset automatically
to a ‘‘0’’ and an interrupt flag (Bit 4, in the Interrupt Status
register) will be generated at the end of the calibration pro-
cedure (4944 clock cycles). After completion of a full auto-
zero and linearity calibration, the Sequencer fetches the
next instruction as pointed to by the Instruction RAM’s
pointer and resumes execution. If the Sequencer is stopped,
a full calibration is performed immediately at the time re-
quested.
Bit 4
is the Standby bit. Writing a ‘‘1’’ to Bit 4 immediately
places the DAS in Standby mode. Normal operation returns
when Bit 4 is reset to a ‘‘0’’. The Standby command (‘‘1’’)
disconnects the external clock from the internal circuitry,
decreases
the
LM12434
and
LM12
à
L
ó
438’s
internal
analog circuitry power supply current, and preserves all in-
ternal RAM contents. After writing a ‘‘0’’ to the Standby bit,
the DAS returns to an operating state identical to that
caused by exercising the RESET bit. A Standby completion
interrupt is issued after a power-up delay to allow the analog
circuitry to settle. The Sequencer should be restarted only
after the Standby completion interrupt is issued (see Note
22). The Instruction RAM can still be accessed through read
and write operations while the LM12434 and LM12
à
L
ó
438
are in Standby Mode.
Bit 5
is the Channel Address Mask. If Bit 5 is set to a ‘‘1’’,
Bits 13–15 in the conversion FIFO will be equal to the sign
bit (Bit 12) of the conversion data. Resetting Bit 5 to a ‘‘0’’
causes conversion data Bits 13 through 15 to hold the in-
struction pointer value of the instruction to which the con-
version data belongs.
Bit 6
selects a ‘‘short’’ auto-zero correction for every con-
version. The Sequencer automatically inserts an auto-zero
before every conversion or ‘‘watchdog’’ comparison if Bit 6
is set to ‘‘1’’. No automatic correction will be performed if Bit
6 is reset to ‘‘0’’.
The DAS’ offset voltage, after calibration, has a typical drift
of 0.1 LSB over a temperature range of
b
40
§
C to
a
85
§
C.
This small drift is less than the variability of the change in
offset that can occur when using the auto-zero correction
with each conversion. This variability is the result of using
only one sample of the offset voltage to create a correction
value. This variability decreases when using the full calibra-
tion mode because eight samples of the offset voltage are
taken, averaged, and used to create a correction value.
Therefore, it is recommended that this mode not be used.
Bit 7
programs the SYNC pin (29) to operate as either an
input or an output. The SYNC pin becomes an output when
Bit 7 is a ‘‘1’’ and an input when Bit 7 is a ‘‘0’’. With SYNC
programmed as an input, the rising edge of any logic signal
applied to pin 29 will start a conversion or ‘‘watchdog’’ com-
parison. Programmed as an output, the logic level at pin 29
will go high at the start of a conversion or ‘‘watchdog’’ com-
parison and remain high until either have finished. See In-
struction RAM ‘‘00’’, Bit 8.
Bits 8
and
9
form the RAM Pointer that is used to select
each of a 48-bit instruction’s three 16-bit sections during
read or write actions. A ‘‘00’’ selects Instruction RAM sec-
tion one, ‘‘01’’ selects section two, and ‘‘10’’ selects section
three.
Bit 10
activates the Test mode that is used only during pro-
duction testing. Always write ‘‘0’’ in this bit when program-
ming the Instruction Register.
Bit 11
is the Diagnostic bit and is available only in the
LM12
à
L
ó
438. It can be activated by setting it to a ‘‘1’’. The
Diagnostic mode, along with a properly chosen instruction,
allows verification that the LM12
à
L
ó
438’s ADC is perform-
ing correctly. When activated, the inverting and non-invert-
ing inputs are connected as shown in Table V. As an exam-
ple, an instruction with ‘‘001’’ for both IN
a
and IN
b
while
using the Diagnostic mode typically results in a full-scale
output.
6.2.3 Interrupts
The LM12434 and LM12
à
L
ó
438 have seven possible inter-
rupts, all with the same priority. Any of these interrupts will
cause a hardware interrupt to appear on the INT pin (31) if
36
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