參數(shù)資料
型號(hào)： LM12434CIV
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： Sign Data Acquisition System with Serial I/O and Self-Calibration
中文描述： SPECIALTY ANALOG CIRCUIT, PQCC28
封裝： PLASTIC, LCC-28
文件頁(yè)數(shù)： 24/80頁(yè)
文件大?。?/td> 1561K
代理商： LM12434CIV
5.0 Pin Descriptions
(Continued)
TABLE I. LM12
à
L
ó
438 Pin Description
(Continued)
Pin Number
Pin Name
Description
PLCC
Pkg.
SO
Pkg.
20
26
P2
Serial interface input:
Standard:
8051:
I
2
C:
TMS320:
CS
1
SAD1
FSX
21
27
P1
Serial interface input:
Standard:
8051:
I
2
C:
TMS320:
R/F (Clock rise/fall)
1
SAD0
FSR
22
23
28
1
MODESEL2
MODESEL1
Serial mode selection inputs. The logic states of these inputs determine the operation of
the serial mode as shown below. The standard mode covers the National’s MICROWIRE,
Motorola’s SPI and Hitachi’s SCl protocols.
MODESEL1, MODESEL2:
01
00
10
11
Standard mode
8051
I
2
C
TMS320
24
2
CLK
The device main clock input. The operating range of clock frequency is 0.05 MHz to
10.0 MHz. The device accuracy is guaranteed only for the clock frequencies indicated in
the specification tables.
25
3
INT
Interrupt output. This is an active low output. An interrupt is generated any time a non-
masked interrupt condition takes place. There are seven different conditions that can
generate an interrupt. (Refer to Section 6.2.4). The interrupt is set high (inactive) by reading
the interrupt status register. This output can drive up to 100 pF of capacitive loads. An
external buffer should be used for driving higher capacitive loads.
26
4
SYNC
Synchronization input/output. SYNC is an input if the Configuration Register’s SYNC I/O bit
is ‘‘0’’ and output when the bit is ‘‘1’’. When sync is an input, a rising edge on this pin
causes the internal S/H to hold the input signal and a conversion cycle or a comparison
cycle (depending on the programmed instruction) to be started. (The conversion or
comparison actually begins on the rising edge of the CLK immediately following the rising
edge of sync.) When output, it goes high at the start of a conversion or a comparison cycle
and returns low when the cycle is completed. At power up the SYNC pin is set as an input.
When used as an output it can drive up to 100 pF of capacitive loads. An external buffer
should be used for driving higher capacitive loads.
27
5
STANDBYOUT
Stand-by output. This is an active low output. STANDBYOUT will be activated when the
LM12
à
L
ó
438 is put into stand-by mode through the Configuration Register’s stand-by bit. It
is used to force any other devices in the system (signal conditioning circuitry, for example)
to go into power-down mode. This is done by connecting the ‘‘shutdown’’, ‘‘powerdown’’,
‘‘standby’’, etc. pins of the other ICs to STANDBYOUT. In those cases where the peripheral
ICs do not have the power-down inputs, STANDBYOUT can be used to turn off their power
through an electronic switch. Note that the logic polarity of the STANDBYOUT is the
opposite to that of the stand-by bit in the Configuration Register.
28
6
V
D
a
Digital supply. See above definition.
LM12434 Pin Description. (Same as LM12
à
L
ó
438 with the exceptions of the following pins.)
LM12434 Pin Description
(Same As LM12
à
L
ó
438 with the exception of the following pins.)
6
7
12
13
MUXOUT
b
MUXOUT
a
Multiplexer outputs. These are the LM12434’s externally available analog MUX output pins.
Analog inputs are directed to these outputs based on the Instruction RAM programming.
8
9
14
15
S/H IN
b
S/H IN
a
Sample-and-hold inputs. These are the inverting and non-inverting inputs of the sample-
and-hold. LM12434 allows external analog signal conditioning circuits to be placed
between MUX outputs and S/H inputs.
24
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