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參數(shù)資料
| 型號： | LM12434CIV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Sign Data Acquisition System with Serial I/O and Self-Calibration |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 30/80頁 |
| 文件大?。?/td> | 1561K |
| 代理商： | LM12434CIV |
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6.0 Operational Information
(Continued)
A4 A3 A2 A1
Purpose
Type D15 D14 D13 D12
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
to
1
0
Instruction RAM
(RAM Pointer
e
00)
R/W
Acquisition
Time
Watch-
dog
S/H IN
b
(MUXIN
b
)
*
S/H IN
a
(MUXIN
a
)
*
8/12 Timer Sync
Pause
Loop
0
1
1
0
0
0
to
1
0
Instruction RAM
(RAM Pointer
e
01)
R/W
Don’t Care
l
/
k
Sign
Limit
Y
1
0
1
1
0
0
0
to
1
0
Instruction RAM
(RAM Pointer
e
10)
R/W
Don’t Care
l
/
k
Sign
Limit
Y
2
0
1
1
1
0
0
0
Configuration
Register
R/W
Don’t Care
DIAG
2
Test
e
0
RAM
Pointer
SYNC A/Z Each
I/O
I/S
Stand-
by
Full
CAL
Auto-
Zero
Reset
Start
Cycle
Interrupt Enable
Register
R/W
Generate Interrupt (INT2)
Number of Conversion
Results in FIFO to
Instruction
Number to
Generate
Interrupt (INT1)
INT7
X
INT5
INT4
INT3
INT2
INT1
INT0
1
0
0
1
Interrupt Status
Register
R
Conversion Results
in FIFO
Number of Unread
Instruction
Number
being
Executed
INST7
X
INST5 INST4 INST3 INST2 INST1 INST0
1
0
1
0
1
0
1
1
Timer
Register
R/W
Timer Preset High Byte
Timer Preset Low Byte
1
1
0
0
Conversion
FIFO
R
Instruction
Number or
Extended
Sign
Sign
Data: MSBs
Conversion
Conversion Data: LSBs
1
1
0
1
Limit Status
Register
R
Limit
Y
2: Status
Limit
Y
1: Status
*
LM12434 (Refer to Table IV).
2
LM12
à
L
ó
438 only. Must be set to ‘‘0’’ for the LM12434.
X No interrupt is associated with this bit. When programming the interrupt Enable Register, bit-6 is a don’t care condition.
FIGURE 9. Bit Assignments for LM12434 and LM12
à
L
ó
438 Internal Registers
30
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相關(guān)代理商/技術(shù)參數(shù) |
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