參數(shù)資料
型號(hào)： LH540215
廠商： Sharp Corporation
英文描述： 512 x 18 / 1024 x 18 Synchronous FIFO
中文描述： 512 ×一千〇二十四分之一十八× 18同步FIFO
文件頁(yè)數(shù)： 7/48頁(yè)
文件大?。?/td> 423K
代理商： LH540215
PIN DESCRIPTIONS (cont’d)
PIN
NAME
PIN
TYPE
1
DESCRIPTION
LD
Load
I
When LD is LOW, the data word on D
0
– D
17
(the data inputs) is written into a
programmable-flag-offset register,
or into the Control Register (when in the
Enhanced Operating Mode),
on the LOW-to-HIGH transition of WCLK, whenever
WEN is LOW. (See Table 3.) Also, when LD is LOW, a word is read to Q
0
– Q
17
(the
data outputs) from the offset registers
and/or the Control Register (when in the
Enhanced Operating Mode)
on the LOW-to-HIGH transition of RCLK, whenever
REN is LOW. (See again Table 3, and particularly the Notes following this table.)
When LD is HIGH, normal FIFO write and read operations are enabled.
In the standalone or paralleled configuration, FL/
RT
should be LOW during a reset
operation. (See Tables 1 and 2.)
However, thereafter, in the standalone or
paralleled configuration, if FL is taken HIGH, it functions instead as RT
(Retransmit), and resets the FIFO’s internal read pointer to the first physical
location of the RAM array. Note that although Retransmit is an ‘enhanced’
feature, it is always available for a FIFO during standalone operation, whether
the FIFO is in IDT-Compatible Operating Mode or in Enhanced Operating
Mode; it is not regulated either by the Control Register or by the EMODE
control input.
In IDT-compatible cascaded configuration, FL has an entirely
different function; it is grounded for the first FIFO device (the ‘master’ device or ‘first-
load’ device), and is set to HIGH for all other FIFO devices in the daisy chain. Thus,
the
Retransmit
feature is not available for FIFOs operating in an IDT-compatible
cascaded configuration.
This signal is dual-purpose; its functionality is determined during a reset operation,
according to its own state, and also according to the states of the three other
control inputs RXI
/REN
2
,
FL
/RT
, and
EMODE
. (See Tables 1 and 2.) In the
standalone or paralleled configuration, WXI/
WEN
2
is grounded. In the cascaded
configuration, WXI/
WEN
2
is connected to WXO (Write Expansion Output) of the
previous device, and functions as WXI.
In the Enhanced Operating Mode,
WXI/WEN
2
functions as a second write-enable signal, WEN
2
, which is ANDed
with WEN to produce an effective internal write-enable signal.
This signal is dual-purpose; its functionality is determined during a reset operation,
according to its own state, and also according to the states of the three other
control inputs WXI
/WEN
2
, FL
/RT
, and
EMODE
. (See Tables 1 and 2.) In the
standalone or paralleled configuration, RXI/
REN
2
is grounded. In the cascaded
configuration, RXI/
REN
2
is connected to
RXO (Read Expansion Output) of the
previous device, and functions as RXI.
In the Enhanced Operating Mode,
RXI/REN
2
functions as a second read-enable signal,
REN
2
, which is ANDed
with REN – and perhaps also with OE, if Control-Register bit 05 is HIGH – to
produce an effective internal read-enable signal.
When FF is LOW, the FIFO is full; further advancement of its internal write-address
pointer, and further data writes through its Data Inputs into its internal memory
array, are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to
WCLK.
When PAF is LOW, the FIFO is ‘a(chǎn)lmost full,’ based on the almost-full-offset value
programmed into the FIFO’s Almost-Full Offset Register. The default value of this
offset at reset is one-eighth of the total number of words in the FIFO-memory array,
minus one, measured from ‘full.’ (See Table 4.) In the IDT-Compatible Operating
Mode, PAF is asynchronous.
In the Enhanced Operating Mode, PAF is
synchronized to WCLK after a reset operation, according to the state of
Control Register bit 04. (See Table 5.)
FL
/RT
First Load/
Retransmit
I
WXI
/WEN
2
Write
Expansion
Input/
Write
Enable 2
I
RXI
/REN
2
Read
Expansion
Input/
Read
Enable 2
I
FF
Full Flag
O
PAF
Programmable
Almost-Full Flag
O
NOTES:
1.
I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
2.
The ostensible differences in signal assertiveness are reconciled before ANDing.
BOLD ITALIC = Enhanced Operating Mode
512 x 18/1024 x 18 Synchronous FIFO
LH540215/25
7
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