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參數(shù)資料
| 型號： | LH540205 |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 8192 x 9 Asynchronous FIFO |
| 中文描述： | 8192 × 9的CMOS異步FIFO |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 136K |
| 代理商： | LH540205 |
The Reset (RS) control signal returns the LH540205
to an initial state, empty and ready to be filled. An
LH540205 should be reset during every system power-up
sequence. A reset operation causes the internal FIFO-
memory-array write-address pointer, as well as the read-
address pointer, to be set back to zero, to point to the
LH540205’s first physical memory location. Any informa-
tion which previously had been stored within the
LH540205 is not recoverable after a reset operation.
A cascading (depth-expansion) scheme may be imple-
mented by using the Expansion In (XI) input signal and
the Expansion Out (XO/HF) output signal. This scheme
allows a deeper ‘effective FIFO’ to be implemented by
using two or more individual LH540205 devices, without
incurring additional latency (‘fallthrough’ or ‘bub-
blethrough’) delays, and without the necessity of storing
and retrieving any given data word more than once. In this
cascaded operating mode, one LH540205 device must
be designated as the ‘first-load’ or ‘master’ device, by
grounding its First-Load (FL/RT) control input; the remain-
ing LH540205 devices are designated as ‘slaves,’ by tying
their FL/RT inputs HIGH. Because of the need to share
control signals on pins, the Half-Full Flag and the retrans-
mission capability are not available for either ‘master’ or
‘slave’ LH540205 devices operating in cascaded mode.
FUNCTIONAL DESCRIPTION (cont’d)
DATA OUTPUTS
Q
0
- Q
8
FLAG
LOGIC
EXPANSION
LOGIC
WRITE
POINTER
INPUT
PORT
CONTROL
READ
POINTER
DATA INPUTS
D
0
- D
8
DUAL-PORT
RAM
ARRAY
8192 x 9
R
W
XO/HF
XI
FL/RT
EF
FF
. . .
540205-1
RESET
LOGIC
RS
OUTPUT
PORT
CONTROL
Figure 2. LH540205 Block Diagram
LH540205
CMOS 8192
×
9 Asynchronous FIFO
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH540215 | 512 x 18 / 1024 x 18 Synchronous FIFO |
| LH540235 | 2048 x 18 / 4096 x 18 Synchronous FIFOs |
| LH5420 | 256 x 36 x 2 Bidirectional FIFO |
| LH5424-S | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
| LH5424-QT | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH540205-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540205-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540205-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540205-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540205-65 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
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