參數(shù)資料
型號(hào): LH51BV1000J
廠商: Sharp Corporation
英文描述: CMOS 1M (128K x8) Static Ram(CMOS 1M (128K x8) 靜態(tài)Ram)
中文描述: 100萬(wàn)的CMOS(128K的× 8)靜態(tài)隨機(jī)存儲(chǔ)器(100萬(wàn)的CMOS(128K的× 8)靜態(tài)羊)
文件頁(yè)數(shù): 8/11頁(yè)
文件大?。?/td> 77K
代理商: LH51BV1000J
DATA VALID
t
DH
t
DW
WE
D
IN
t
CW
ADDRESS
t
WC
51BV1000-5
t
WR
CE
1
CE
2
t
AS
t
WZ
t
WP
(NOTE 2
)
(NOTE 4)
t
WR
(NOTE 3)
D
OUT
(NOTE 6)
(NOTE 1)
t
WR
t
OW
(NOTE 7)
1. A write occurs during the overlap of a LOW CE
1
, a HIGH CE
2
and a LOW WE,
A write begins at the latest transition among CE
1
going LOW, CE
2
going HIGH
and WE going LOW. A write ends at the earliest transition among CE
1
going
HIGH. CE
2
going LOW and WE going HIGH. t
WP
is measured from the beginning
of write to the end of write.
2. t
is measured from the latter of CE
1
going LOW or CE
2
going HIGH to the
end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR1
applies
in case a write ends at CE
1
or WE going HIGH. t
WR2
applies in case a write
ends at CE
2
going LOW.
5. During this period, I/O pins are in the output state, therefore the input signals
of opposite phase to the outputs must not be applied.
6. If CE
goes LOW simultaneously with WE going LOW or after WE going LOW,
the outputs remain in high impedance state.
7. If CE
1
goes HIGH simulaneously with WE going HIGH or before WE going HIGH,
the outputs remain in high impedance state.
NOTES:
t
CW
(NOTE 2
)
(NOTE 5)
t
AW
Figure 5. Write Cycle (OE Low Fixed)
LH51BV1000J
CMOS 1M (128K
×
8) Static RAM
8
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