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參數(shù)資料
| 型號： | LH51BV1000J |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 1M (128K x8) Static Ram(CMOS 1M (128K x8) 靜態(tài)Ram) |
| 中文描述： | 100萬的CMOS（128K的× 8）靜態(tài)隨機存儲器（100萬的CMOS（128K的× 8）靜態(tài)羊） |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 77K |
| 代理商： | LH51BV1000J |
D
IN
51BV1000-4
ADDRESS
OE
t
WC
t
WR
t
CW
t
CW
t
WR
t
AS
t
WP
t
OHZ
t
DW
t
WR
t
DH
DATA VALID
CE
1
CE
2
WE
D
OUT
1. A write occurs during the overlap of a LOW CE
1
, a HIGH CE
2
and a LOW WE,
A write begins at the latest transition among CE
1
going LOW, CE
2
going HIGH
and WE going LOW. A write ends at the earliest transition among CE
1
going
HIGH, CE
2
going LOW and WE going HIGH. t
WP
is measured from the beginning
of write to the end of write.
2. t
CW
is measured from the latter of CE
1
going LOW or CE
2
going HIGH to the
end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR1
applies
in case a write ends at CE
1
or WE going HIGH. t
WR2
applies in case a write
ends at CE
2
going LOW.
5. During this period, I/O pins are in the output state, therefore the input signals
of opposite phase to the outputs must not be applied.
6. If CE
1
goes LOW simultaneously with WE going LOW or after WE going LOW,
the outputs remain in high impedance state.
7. If CE
1
goes HIGH simulaneously with WE going HIGH or before WE going HIGH,
the outputs remain in high impedance state.
NOTES:
(NOTE 4)
(NOTE 2)
(NOTE 2)
(NOTE 1)
(NOTE 3)
(NOTE 6)
(NOTE 5)
t
AW
Figure 4. Write Cycle (OE Controlled)
CMOS 1M (128K
×
8) Static RAM
LH51BV1000J
7
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相關代理商/技術參數(shù) |
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|---|---|
| LH51BV1000JY-70LL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LH51V1032C4M-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| LH51V1032C4M-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| LH51V2016J85LL | 制造商:Sharp Microelectronics Corporation 功能描述: |
| LH51V2016JY-85LL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
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