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參數(shù)資料
| 型號： | LH28F640BFHE-PTTL80 |
| 英文描述： | Flash ROM |
| 中文描述： | 閃存ROM |
| 文件頁數(shù)： | 33/56頁 |
| 文件大?。?/td> | 373K |
| 代理商： | LH28F640BFHE-PTTL80 |
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- 33 -
5 DESIGN CONSIDERATIONS
5.1
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Three-
line control provides for :
Three-Line Output Control
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2
STS and Block Erase, Full Chip
Erase, (Multi) Word/Byte Write and
Block Lock-Bit Configuration Polling
STS is an open drain output that should be
connected to V
CC
by a pullup resistor to provide a
hardware method of detecting block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration completion. In default mode, it
transitions low after block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
commands and returns to V
OH
when the WSM has
finished executing the internal algorithm. For
alternate STS pin configurations, see the Configu-
ration command (
Table 3
and
Section 4.14
).
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the
device is in block erase suspend (with (multi)
word/byte write inactive), (multi) word/byte write
suspend or deep power-down modes.
5.3
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 μF ceramic capacitor connected
between its V
CC
and GND and between its V
PP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 μF electrolytic capacitor should be placed at
the array’s power supply connection between V
CC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
Power Supply Decoupling
5.4
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the V
PP
power supply
trace. The V
PP
pin supplies the memory cell current
for block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration. Use similar
trace widths and layout considerations given to the
V
CC
power bus. Adequate V
PP
supply traces and
decoupling will decrease V
PP
voltage spikes and
overshoots.
V
PP
Trace on Printed Circuit Boards
5.5
Block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration are not guaranteed
if V
PP
falls outside of a valid V
PPH1
range, V
CC
falls
outside of a valid V
CC1/2
range, or RP# = V
IL
. If
V
PP
error is detected, status register bit SR.3 is set
to "1" along with SR.4 or SR.5, depending on the
attempted operation. If RP# transitions to V
IL
during
block erase, full chip erase, (multi) word/byte write
or block lock-bit configuration, STS (if set to
V
CC
, V
PP
, RP# Transitions
LH28F160S5-L/S5H-L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH28F640BFHE-PTTLHGA | 制造商:Sharp Microelectronics Corporation 功能描述:64M (4MX16) 3V, BOOT BLOCK, TOP, TSOP48, IND, HAZMAT - Trays |
| LH28F640BFHG-PBTLZ7 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:64M (x16) Flash Memory |
| LH28F640SP | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:64Mbit (4Mbitx16/8Mbitx8) Page Flash Memory |
| LH28F640SPHT-PL12A | 功能描述:閃存 64MB X8/X16 3V DUAL SUPPLY RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| LH28F640SPHT-PTL12 | 功能描述:IC FLASH 64MBIT 120NS 56TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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